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Thread warping: A framework for dynamic synthesis of thread accelerators

Thread warping: A framework for dynamic synthesis of thread ...

引用

codes+isss 2007: 5th international conference on hardware/software codesign and system synthesis

作者： Stitt, Greg Vahid, Frank Department of Electrical and Computer Engineering University of Florida Department of Computer Science and Engineering University of California Riverside

ISBN: (纸本)9781595938244

We present a dynamic optimization technique, thread warping, that uses a single processor on a multiprocessor system to dynamically synthesize threads into custom accelerator circuits on FPGAs (field-programmable gate arrays). Building on dynamic synthesis for single-processor single-thread systems, known as warp processing, thread warping improves performances of multiprocessor systems by speeding up individual threads and by allowing more threads to execute concurrently. Furthermore, thread warping maintains the important separation of function from architecture, enabling portability of applications to architectures with different quantities of microprocessors and *** advantage not shared by static compilation/synthesis approaches. We introduce a framework of architecture, CAD tools, and operating system that together support thread warping. We summarize experiments on an extensive architectural simulation framework we developed, showing application speedups of 4x to 502x, averaging 130x compared to a multiprocessor system having four ARM11 microprocessors, for eight benchmark applications. Even compared to a 64-processor system, thread warping achieves 11x speedup. Copyright 2007 ACM.

关键词： Spinning (fibers)

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Embedded software development on top of transaction-level models

Embedded software development on top of transaction-level mo...

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codes+isss 2007: 5th international conference on hardware/software codesign and system synthesis

作者： Klingauf, Wolfgang Günzel, Robert Schröder, Christian Technical University of Braunschweig Dept. E.I.S. Mühlenpfordtstr. 23 38106 Braunschweig Germany

ISBN: (纸本)9781595938244

Early embedded SW development with transaction-level models has been broadly promoted to improve SoC design productivity. But the proposed APIs only provide low-level read/write operations via a TLM interconnect. SW developers have to implement platform-specific communication procedures and handshake protocols to access HW functions, which requires a deep understanding of both the HW interfaces and the TLM fabric used. In this paper, we propose our concept of hardware procedure calls (HPC) with which HW services are provided to SW processes as remote methods on top of transaction-level communication. To this end, a lightweight HPC protocol is presented, and we propose a method to generate the infrastructure for HPC communication from a straightforward input description. Our experiments show that with HPC, embedded SW development is considerably made easier, and that also the effort to create the transaction-level model itself is reduced. Copyright 2007 ACM.

关键词： Middleware

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ESL design and HW/SW co-verification of high-end software defined radio platforms

ESL design and HW/SW co-verification of high-end software de...

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codes+isss 2007: 5th international conference on hardware/software codesign and system synthesis

作者： Ng, A.C.H. Weijers, J.W. Glassee, M. Schuster, T. Bougard, B. Van Der Perre, L. IMEC Belgium

ISBN: (纸本)9781595938244

Multiple wireless technologies are converging to run on personal handhelds. The plethora of communication standards next to the cost issues of deeper submicron processing require handheld platforms to shift from sets of multiple application specific ICs (ASICs) to multi-purpose Multi-Processor system-on-Chip (MPSoC) on which software Defined Radios (SDR) are run. SDR design faces hard real-time processing and data transfer latency constraints. Designing SDR under stringent time-to-market (cost), energy and real-time processing constraints requires the help of advanced Electronic system-Level (ESL) design methodologies. This paper demonstrates an integrated ESL design flow built on advanced ESL tools to design SDR platforms for handhelds. We share the experience from creation of a high-level virtual platform model down to hardware/software (HW/SW) co-verification of a large scale SoC (5 million gates+). Incremental RTL verification based on co-simulation and co-emulation is also presented. Copyright 2007 ACM.

关键词： Computer software

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Energy efficient co-scheduling in dynamically reconfigurable systems

Energy efficient co-scheduling in dynamically reconfigurable...

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codes+isss 2007: 5th international conference on hardware/software codesign and system synthesis

作者： Hsiung, Pao-Ann Lu, Pin-Hsien Liu, Chih-Wen Department of Computer Science and Information Engineering National Chung Cheng University Chiayi 62102 Taiwan

ISBN: (纸本)9781595938244

Energy consumption is a major issue in dynamically reconfigurable systems because of the high power requirements during repeated configurations. hardware designs employ low power techniques such as configuration prefetch and reuse. software designs restrain energy usage by dynamically scaling the voltage of processors. However, when these techniques are implemented in a system, they might be conflicting and thus cancel their mutual benefits, which results in high power consumption and low performance. We propose run-time co-scheduling of hardware and software tasks by using the slack time, which is introduced due to reusing hardware task configurations, for dynamically scaling the processor voltage such that preceding software tasks consume lesser power. At the same time, the reuse of hardware task configurations also result in lower power consumption and higher performance due to fewer number of reconfigurations. The combined effects of hardware configuration reuse and software dynamic voltage scaling result in schedules with a lower power consumption and higher performance than that obtained through individual techniques applied to hardware and software separately. We performed extensive experiments whose results show that irrespective of different slack ratios, number of voltage levels, or hardware partitions, the schedules generated by our proposed method are more energy efficient than methods that either do not apply any runtime techniques or only apply hardware configuration prefetch and reuse. Copyright 2007 ACM.

关键词： software design

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Probabilistic performance risk analysis at system-level

Probabilistic performance risk analysis at system-level

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codes+isss 2007: 5th international conference on hardware/software codesign and system synthesis

作者： Viehl, Alexander Schwarz, Markus Bringmann, Oliver Rosenstiel, Wolfgang FZI Forschungszentrum Informatik Haid-und-Neu-Str. 10-14 76131 Karlsruhe Germany Universitat Tubingen Sand 13 72076 Tubingen Germany

ISBN: (纸本)9781595938244

We present a novel hybrid approach for performance analysis of a system design. Unlike other approaches in this area, in this paper we do not focus on the determination of pessimistic best-case and worst-case quantities of system properties. Our proposed analysis methodology determines qualitative numbers between best-case and worst-case of system properties and quantifies them with probabilities. For this issue, we combine local coarse-grained profiling and formal system-level analysis models in a hybrid approach for an early quantitative determination of qualitative system properties. Our approach considers the control-flow of communicating processes and the impact of blocking communication instances on the temporal behavior of the entire system during formal analysis. This can be used for determining the global system performance. The application of our new methodology leads to an inclusion of probabilities concerning system properties and allows an early performance risk estimation of a design with regard to predefined system requirements and constraints. Copyright 2007 ACM.

关键词： Risk analysis

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A data protection unit for NoC-based architectures

A data protection unit for NoC-based architectures

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codes+isss 2007: 5th international conference on hardware/software codesign and system synthesis

作者： Fiorin, Leandro Palermo, Gianluca Lukovic, Slobodan Silvano, Cristina ALaRI Faculty of Informatics University of Lugano Via Buffi 13 6904 Lugano Switzerland Politecnico di Milano Dipartimento di Elettronica e Informazione Via Ponzio 34/5 20133 Milano Italy

ISBN: (纸本)9781595938244

Security is gaining increasing relevance in the development of embedded devices. Towards a secure system at each level of design, this paper addresses the security aspects related to Network-on-Chip (NoC) architectures, foreseen as the communication infrastructure of next-generation embedded devices. In the context of NoC-based Multiprocessor systems, we focus on the topic, not thoroughly faced yet, of data protection. We present the architecture of a Data Protection Unit (DPU) designed for implementation within the Network Interface (NI). The DPU supports the capability to check and limit the access rights (none, read, write or both) of processors requesting access to data locations in a shared memory - in particular distinguishing between the operating roles (supervisor or user) of processing elements. We explore different alternative implementations and demonstrate how the DPU unit does not affect the network latency if the memory request has the appropriate rights. In the experimental section we show synthesis results for different ASIC implementations of the Data Protection Unit. Copyright 2007 ACM.

关键词： software architecture

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Dynamic security domain scaling on symmetric multiprocessors for future high-end embedded systems

Dynamic security domain scaling on symmetric multiprocessors...

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codes+isss 2007: 5th international conference on hardware/software codesign and system synthesis

作者： Inoue, Hiroaki Ikeno, Akihisa Abe, Tsuyoshi Sakai, Junji Edahiro, Masato System IP Core Research Laboratories NEC Corporation 1120 Shimokuzawa Sagamihara Kanagawa 229-1198 Japan NEC Informatec Systems Ltd. 3-2-1 Sakado Takatsu-ku Kawasaki Kanagawa 213-0012 Japan

ISBN: (纸本)9781595938244

We propose a method for dynamic security domain scaling on SMPs that offers both highly scalable performance and high security for future high-end embedded systems. Its most important feature is its highly efficient use of processor resources, accomplished by dynamically changing the number of processors within a security domain in response to application load requirements. Two new technologies make this scaling possible without any virtualization software: 1) self-transition management and 2) unified virtual address mapping. Evaluations show that this domain control provides highly scalable performance and incurs almost no performance overhead in security domains. The increase in binary code size is less than 40KB, and the time required for individual state transitions is of a single-millisecond order. This scaling is the first in the world to make possible dynamic changing of the number of processors within a security domain on an ARM SMP. Copyright 2007 ACM.

关键词： Security of data

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A code-generator generator for multi-output instructions

A code-generator generator for multi-output instructions

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codes+isss 2007: 5th international conference on hardware/software codesign and system synthesis

作者： Scharwaechter, Hanno Leupers, Rainer Ascheid, Gerd Meyr, Heinrich Youn, Jonghee M. Paek, Yunheung Integrated Signal Processing Systems RWTH Aachen University Germany Software Optimization and Restructuring Research Group Seoul National University Korea Republic of

ISBN: (纸本)9781595938244

We address the problem of instruction selection for Multi-Output Instructions (MOIs), producing more than one result. Such inherently parallel hardware instructions are very common in the area of Application Specific Instruction Set Processors (ASIPs) and Digital Signal Processors (DSPs) which are frequently used in system-on-Chips as programmable cores. In order to provide high-level programmability, and consequently guarantee widespread acceptance, sophisticated compiler support for these programmable cores is of high importance. Since it is not possible to model Multi-Output Instructions as trees in the compiler's Intermediate Representation (IR), traditional approaches for code selection are not sufficient. Extending traditional code-generation approaches for MOI-selection is essentially a graph covering problem, which is known to be NP-complete. We present a new heuristic algorithm incorporated in a retargetable code-generator generator capable of exploiting arbitrary inherently parallel MOIs. We prove the concept by integrating the tool into the LCC compiler which has been targeted towards different Instruction Set Architectures based on the MIPS architecture. Several network applications as well as some DSP benchmarks were compiled and evaluated to obtain results. Copyright 2007 ACM.

关键词： Automatic programming

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Three-dimensional multiprocessor system-on-chip thermal optimization

Three-dimensional multiprocessor system-on-chip thermal opti...

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codes+isss 2007: 5th international conference on hardware/software codesign and system synthesis

作者： Sun, Chong Shang, Li Dick, Robert P. ECE Department Queen's University Kingston ON K7L 3N6 Canada EECS Department Northwestern University Evanston IL 60208 United States

ISBN: (纸本)9781595938244

3D stacked wafer integration has the potential to improve multiprocessor system-on-chip (MPSoC) integration density, performance, and power efficiency. However, the power density of 3D MPSoCs increases with the number of active layers, resulting in high chip temperatures. This can reduce system reliability, reduce performance, and increase cooling cost. Thermal optimization for 3D MPSoCs imposes numerous challenges. It is difficult to manage assignment and scheduling of heterogeneous workloads to maintain thermal safety. In addition, the thermal characteristics of 3D MPSoCs differ from those of 2D MPSoCs because each stacked layer has a different thermal resistance to the ambient and vertically-adjacent processors have strong temperature correlation. We propose a 3D MPSoC thermal optimization algorithm that conducts task assignment, scheduling, and voltage scaling. A power balancing algorithm is initially used to distribute tasks among cores and active layers. Detailed thermal analysis is used to guide a hotspot mitigation algorithm that incrementally reduces the peak MPSoC temperature by appropriately adjusting task execution times and voltage levels. The proposed algorithm considers leakage power consumption and adapts to inter-layer thermal heterogeneity. Performance evaluation on a set of multiprogrammed and multithreaded benchmarks indicates that the proposed techniques can optimize 3DMPSoC power consumption, power profile, and chip peak temperature. Copyright 2007 ACM.

关键词： Multiprocessing systems

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Bridging gap between simulation and spreadsheet study

Bridging gap between simulation and spreadsheet study

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international conference on hardware/software codesign and system synthesis (codes)

作者： Antoine Perrin Frank Ghenassia STMicroelectronics Grenoble France

system architects working on SoC design have traditionally been hampered by the lack of a cohesive methodology for architecture evaluation and co-verification of hardware and software. This paper focuses on a comprehensive analysis framework providing platform assembly facilities, system analysis tools, enhanced traffic model and systemC TLM IP. This framework has been intensively used to design and analyze complex SOC Interconnect based on STBus protocol such as the one of 71xx families. By hiding the complexity of a simulation and filling the gap towards spreadsheet study and costly On-Chip analysis using traffic model, architects benefit from an easy access to an efficient simulation for performance evaluation.

关键词： system-on-a-chip Analytical models Computer architecture Generators Real time systems Bridges Filling

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