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Energy efficient co-scheduling in dynamically reconfigurable systems

Energy efficient co-scheduling in dynamically reconfigurable...

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international conference on hardware/software codesign and system synthesis (codes)

作者： Pao-Ann Hsiung Pin-Hsien Lu Chih-Wen Liu Department of Computer Science and Information Engineering National Chung Cheng University Chiayi Taiwan

Energy consumption is a major issue in dynamically reconfigurable systems because of the high power requirements during repeated configurations. hardware designs employ low power techniques such as configuration prefetch and reuse. software designs restrain energy usage by dynamically scaling the voltage of processors. However, when these techniques are implemented in a system, they might be conflicting and thus cancel their mutual benefits, which results in high power consumption and low performance. We propose run-time co-scheduling of hardware and software tasks by using the slack time, which is introduced due to reusing hardware task configurations, for dynamically scaling the processor voltage such that preceding software tasks consume lesser power. At the same time, the reuse of hardware task configurations also result in lower power consumption and higher performance due to fewer number of reconfigurations. The combined effects of hardware configuration reuse and software dynamic voltage scaling result in schedules with a lower power consumption and higher performance than that obtained through individual techniques applied to hardware and software separately. We performed extensive experiments whose results show that irrespective of different slack ratios, number of voltage levels, or hardware partitions, the schedules generated by our proposed method are more energy efficient than methods that either do not apply any runtime techniques or only apply hardware configuration prefetch and reuse.

关键词： hardware Dynamic scheduling Prefetching Processor scheduling Voltage control

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Complex task activation schemes in system level performance analysis

Complex task activation schemes in system level performance ...

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international conference on hardware/software codesign and system synthesis (codes)

作者： Wolfgang Haid Lothar Thiele Computer Engineering and Networks Laboratory Swiss Federal Institute of Technology Zurich Switzerland

The design and analysis of today's complex real-time systems requires advanced methods. Due to ever growing functionality, hardware complexity and component interaction, applying traditional methods like HW/SW co-simulation is getting increasingly difficult. On the other hand, analytic approaches have proven their usefulness and efficiency for system analysis when end-to-end performance figures like delay, throughput and memory consumption are requested. One of the main drawbacks of these methods is the limited set of systems that can be analyzed with high accuracy: Only simple models for task interaction and task semantics can be used. In this paper, we extend existing methods for analyzing heterogeneous multiprocessor systems such that (a) non-preemptive scheduling policies, (b) complex activation schemes for tasks and (c) conditional behavior of task executions can be modeled and analyzed. We demonstrate the usefulness of the proposed approach in a case study.

关键词： Analytical models Delay Decoding Performance analysis Processor scheduling Embedded systems Algorithm design and analysis

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A framework for rapid system-level exploration, synthesis, and programming of multimedia MP-SoCs

A framework for rapid system-level exploration, synthesis, a...

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international conference on hardware/software codesign and system synthesis (codes)

作者： Mark Thompson Hristo Nikolov Todor Stefanov Andy D. Pimentel Cagkan Erbas Simon Polstra Ed F. Deprettere Department of Computer Science University of Amsterdam Netherlands Leiden Embedded Research Center Leiden University Netherlands

In this paper, we present the Daedalus framework, which allows for traversing the path from sequential application specification to a working MP-SoC prototype in FPGA technology with the (parallelized) application mapped onto it in only a matter of hours. During this traversal, which offers a high degree of automation, guidance is provided by Daedalus' integrated system-level design space exploration environment. We show that Daedalus offers remarkable potentials for quickly experimenting with different MP-SoC architectures and exploring system-level design options during the very early stages of design. Using a case study with a Motion-JPEG encoder application, we illustrate Daedalus' design steps and demonstrate its efficiency.

关键词： Computer architecture Computational modeling Program processors IP networks Field programmable gate arrays XML Space exploration

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Simultaneous synthesis of buses, data mapping and memory allocation for MPSoC

Simultaneous synthesis of buses, data mapping and memory all...

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international conference on hardware/software codesign and system synthesis (codes)

作者： Brett H. Meyer Donald E. Thomas Department of Electrical and Computer Engineering Carnegie Mellon University Pittsburgh PA USA

Heterogeneous multiprocessors are emerging as the dominant implementation approach to embedded multiprocessor systems. In addition to having processing elements suited to the target applications, these systems will also have custom memory and bus architectures. Because of performance and cost constraints, these systems must be carefully designed to balance system partitioning and resource sharing. The sheer size of the design space requires that tools be able to do this balancing. We have developed an augmented simulated annealing synthesis tool that uses system performance and layout evaluation to drive simultaneous data mapping, memory allocation and bus synthesis. Performing these optimizations at the same time, our tool is able to explore a larger design space and take advantage of cost-saving resource sharing unavailable to previous approaches that allocate memories before synthesizing buses. This results in 20% cost reduction for high-performance designs as well as 27% for low-cost designs in comparison with an approach that performs memory allocation and data mapping separately from bus synthesis.

关键词： Resource management Annealing Topology Wire Libraries Limiting Space exploration

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ESL design and HW/SW co-verification of high-end software Defined Radio platforms

ESL design and HW/SW co-verification of high-end Software De...

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international conference on hardware/software codesign and system synthesis (codes)

作者： A. C. H. Ng J. W. Weijers M. Glassee T. Schuster B. Bougard L. Van der Perre IMEC Belgium

Multiple wireless technologies are converging to run on personal handhelds. The plethora of communication standards next to the cost issues of deeper submicron processing require handheld platforms to shift from sets of multiple application specific ICs (ASICs) to multi-purpose Multi-Processor system-on-Chip (MPSoC) on which software Defined Radios (SDR) are run. SDR design faces hard real-time processing and data transfer latency constraints. Designing SDR under stringent time-to-market (cost), energy and real-time processing constraints requires the help of advanced Electronic system-Level (ESL) design methodologies. This paper demonstrates an integrated ESL design flow built on advanced ESL tools to design SDR platforms for handhelds. We share the experience from creation of a high-level virtual platform model down to hardware/software (HW/SW) co-verification of a large scale SoC (5 million gates+). Incremental RTL verification based on co-simulation and co-emulation is also presented.

关键词： hardware design languages Emulation Throughput Time domain analysis Time varying systems Synchronization Gain control

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A data protection unit for NoC-based architectures

A data protection unit for NoC-based architectures

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international conference on hardware/software codesign and system synthesis (codes)

作者： Leandro Fiorin Gianluca Palermo Slobodan Lukovic Cristina Silvano ALaRI-Faculty of Informatics University of Lugano Lugano Switzerland Dipartimento di Elettronica e Informazione Politecnico di Milano Milan Italy

Security is gaining increasing relevance in the development of embedded devices. Towards a secure system at each level of design, this paper addresses the security aspects related to Network-on-Chip (NoC) architectures, foreseen as the communication infrastructure of next-generation embedded devices. In the context of NoC-based Multiprocessor systems, we focus on the topic, not thoroughly faced yet, of data protection. We present the architecture of a Data Protection Unit (DPU) designed for implementation within the Network Interface (NI). The DPU supports the capability to check and limit the access rights (none, read, write or both) of processors requesting access to data locations in a shared memory - in particular distinguishing between the operating roles (supervisor or user) of processing elements. We explore different alternative implementations and demonstrate how the DPU unit does not affect the network latency if the memory request has the appropriate rights. In the experimental section we show synthesis results for different ASIC implementations of the Data Protection Unit.

关键词： Computer architecture Nickel Random access memory Permission Computer aided manufacturing system-on-a-chip

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Dynamic security domain scaling on symmetric multiprocessors for future high-end embedded systems

Dynamic security domain scaling on symmetric multiprocessors...

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international conference on hardware/software codesign and system synthesis (codes)

作者： Hiroaki Inoue Akihisa Ikeno Tsuyoshi Abe Junji Sakai Masato Edahiro Nihon Denki Kabushiki Kaisha Minato-ku Tokyo JP NEC Informatec Systems Ltd. Kawasaki Kanagawa Japan NEC Corporation System IP Core Research Laboratories Sagamihara Kanagawa Japan

We propose a method for dynamic security domain scaling on SMPs that offers both highly scalable performance and high security for future high-end embedded systems. Its most important feature is its highly efficient use of processor resources, accomplished by dynamically changing the number of processors within a security domain in response to application load requirements. Two new technologies make this scaling possible without any virtualization software: 1) self-transition management and 2) unified virtual address mapping. Evaluations show that this domain control provides highly scalable performance and incurs almost no performance overhead in security domains. The increase in binary code size is less than 40 KB, and the time required for individual state transitions is of a single-millisecond order. This scaling is the first in the world to make possible dynamic changing of the number of processors within a security domain on an ARM SMP.

关键词： Security Context Registers Embedded systems Switches Process control

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Thread warping: A framework for dynamic synthesis of thread accelerators

Thread warping: A framework for dynamic synthesis of thread ...

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international conference on hardware/software codesign and system synthesis (codes)

作者： Greg Stitt Frank Vahid Department of Electrical and Computer Engineering University of Florida USA Department of Computer Science and Engineering University of California Riverside USA Center of Embedded Computer Systems University of California Irvine USA

We present a dynamic optimization technique, thread warping, that uses a single processor on a multiprocessor system to dynamically synthesize threads into custom accelerator circuits on FPGAs (field-programmable gate arrays). Building on dynamic synthesis for single-processor single-thread systems, known as warp processing, thread warping improves performances of multiprocessor systems by speeding up individual threads and by allowing more threads to execute concurrently. Furthermore, thread warping maintains the important separation of function from architecture, enabling portability of applications to architectures with different quantities of microprocessors and FPGA-an advantage not shared by static compilation/synthesis approaches. We introduce a framework of architecture, CAD tools, and operating system that together support thread warping. We summarize experiments on an extensive architectural simulation framework we developed, showing application speedups of 4× to 502×, averaging 130× compared to a multiprocessor system having four ARM11 microprocessors, for eight benchmark applications. Even compared to a 64-processor system, thread warping achieves 11× speedup.

关键词： Instruction sets Field programmable gate arrays Design automation Synchronization Microprocessors system-on-a-chip

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Temperature-aware processor frequency assignment for MPSoCs using convex optimization

Temperature-aware processor frequency assignment for MPSoCs ...

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international conference on hardware/software codesign and system synthesis (codes)

作者： Srinivasan Murali Almir Mutapcic David Atienza Rajesh Gupta Stephen Boyd Giovanni De Micheli LSI EPF Lausanne Switzerland Department of Electrical Engineering University of Stanford USA DACYA Complutense University of Madrid Spain Department of Computer Science and Engineering University of California San Diego USA

The increasing processing capability of Multi-Processor systems-on-Chips (MPSoCs) is leading to an increase in chip power dissipation, which in turn leads to significant increase in chip temperature. An important challenge facing the MPSoC designers is to achieve the highest performance system operation that satisfies the temperature and power consumption constraints. The frequency of operation of the different processors and the application workload assignment play a critical role in determining the performance, power consumption and temperature profile of the MPSoC. In this paper, we propose novel convex optimization based methods that solve this important problem of temperature-aware processor frequency assignment, such that the total system performance is maximized and the temperature and power constraints are met. We perform experiments on several realistic SoC benchmarks using a cycle-accurate FPGA-based thermal emulation platform, which show that the systems designed using our methods meet the temperature and power consumption requirements at all time instances, while achieving maximum performance.

关键词： Mathematical model Optimization Power demand Steady-state Time frequency analysis Thermal conductivity system-on-a-chip

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A code-generator generator for Multi-Output Instructions

A code-generator generator for Multi-Output Instructions

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international conference on hardware/software codesign and system synthesis (codes)

作者： Hanno Scharwaechter Rainer Leupers Gerd Ascheid Heinrich Meyr Jonghee M. Youn Yunheung Paek Integrated Signal Processing Systems RWTH Aachen University Germany Software Optimization & Restructuring Research Group Seoul National University South Korea

We address the problem of instruction selection for Multi-Output Instructions (MOIs), producing more than one result. Such inherently parallel hardware instructions are very common in the area of Application Specific Instruction Set Processors (ASIPs) and Digital Signal Processors (DSPs) which are frequently used in system-on-Chips as programmable cores. In order to provide high-level programmability, and consequently guarantee widespread acceptance, sophisticated compiler support for these programmable cores is of high importance. Since it is not possible to model MultiOutput Instructions as trees in the compiler's Intermediate Representation (IR), traditional approaches for code selection are not sufficient. Extending traditional code-generation approaches for MOI-selection is essentially a graph covering problem, which is known to be NP-complete. We present a new heuristic algorithm incorporated in a retargetable code-generator generator capable of exploiting arbitrary inherently parallel MOIs. We prove the concept by integrating the tool into the LCC compiler which has been targeted towards different Instruction Set Architectures based on the MIPS architecture. Several network applications as well as some DSP benchmarks were compiled and evaluated to obtain results.

关键词： Grammar Program processors Generators Assembly Pattern matching Protocols Encryption

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