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2021 international conference on hardware/software codesign and system synthesis, codes+isss 2021

作者： Millican, Spencer Griffith, SueAnne Auburn University Department of Electrical and Computer Engineering Samuel Ginn College of Engineering AuburnAL United States

ISBN: (纸本)9781450390767

This work presents a plan for investigating transistor aging and degradation in cyber physical systems under attack. The authors discuss the importance of such concerns, particularly with regard to negative bias temperature instability, and an approach to demonstrate the adverse effects of a cyber-attack resulting in premature aging of transistors within a system's digital controllers. © 2021 ACM.

关键词： Cyber Physical system

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Special Session: Machine Learning for Embedded system Design

Special Session: Machine Learning for Embedded System Design

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international conference on hardware/software codesign and system synthesis (codes)

作者： Erika S. Alcorta Andreas Gerstlauer Chenhui Deng Qi Sun Zhiru Zhang Ceyu Xu Lisa Wu Wills Daniela Sánchez Lopera Wolfgang Ecker Siddharth Garg Jiang Hu The University of Texas at Austin Austin TX USA Cornell University Ithaca NY USA Duke University Durham NC USA Infineon Technologies AG Technical University of Munich Munich Germany New York University New York NY USA Texas A&M University College Station TX USA

Embedded systems are becoming increasingly complex, which has led to a productivity crisis in their design and verification. Although conventional design automation coupled with IP and platform reuse techniques have led to leaps in design productivity improvement, they face fundamental limits given that most design optimization and verification problems remain NP-hard and that reuse of pre-designed IP blocks and platforms inherently limits flexibility and optimality. At the same time, machine learning (ML) has recently made unprecedented advances and created phenomenal impact in various computing applications. In particular, application of ML techniques as a way to extract knowledge and learn from existing design, optimization and verification data has recently seen a lot of excitement and promise at lower physical and integrated circuit levels of abstraction. Using ML has the potential to similarly close the complexity gap in embedded system design, but corresponding ML-based approaches for embedded system optimization and verification at higher levels of abstraction are still at their infancy. This paper presents the current state of the art, along with opportunities and open challenges, in the application of ML methods for embedded system design and optimization. We discuss design and optimization at different levels of abstraction ranging from system-level modeling and optimization and high-level synthesis to RTL and micro-architecture design, bringing together perspectives from different communities in both academia and industry.

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Tutorial: Large-Scale Spiking Neuromorphic Architecture Exploration using SANA-FE

Tutorial: Large-Scale Spiking Neuromorphic Architecture Expl...

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international conference on hardware/software codesign and system synthesis (codes)

作者： James A. Boyle Mark Plagge Suma G. Cardwell Frances S. Chanc Andreas Gerstlauer The University of Texas at Austin Texas USA Sandia National Laboratories New Mexico USA

ISBN: (数字)9798350356397

ISBN: (纸本)9798350356403

Neuromorphic computing uses brain-inspired concepts to accelerate and efficiently execute a wide range of applications, such as mimicking biological circuits, solving NPhard optimization problems and accelerating machine learning at the edge. In particular, neuromorphic architectures to efficiently execute Spiking Neural Networks (SNNs) have gained popularity. SNNs extend artificial neural networks (ANNs) by encoding information in time as either rates or delays between spiking events, shared between neurons via their weighted connections. SNN-based platforms are event-driven, resulting in naturally sparse, noise-tolerant and power-efficient computation. In this tutorial, we present the state-of-the-art in scalable digital and analog spiking neuromorphic system architectures, and discuss current research trends within the neuromorphic architecture field at the system level. We further introduce our SANA-FE tool for Simulation of Advanced Neuromorphic Architectures for Fast Exploration, which has been developed as part of a collaboration between the University of Texas at Austin and Sandia National Laboratories. SANA-FE allows for modeling and performance-power prediction of different spiking hardware architectures executing SNN applications to support rapid, early system-level design-space exploration, hardware-aware application development and system architecture co-design. The tutorial includes a hands-on component in which SANA-FE’s capabilities are demonstrated and used to perform system design and application mapping case studies.

关键词： Neuromorphic engineering Neurons systems architecture Computer architecture Tutorials Spiking neural networks Predictive models Market research system analysis and design Optimization

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2016 international conference on hardware/software codesign and system synthesis, codes+isss 2016

2016 International Conference on Hardware/Software Codesign ...

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2016 international conference on hardware/software codesign and system synthesis, codes+isss 2016

ISBN: (纸本)9781450330503

The proceedings contain 37 papers. The topics discussed include: a practical methodology to validate the statistical behavior of bloom filters;scalable and realistic benchmark synthesis for efficient NoC performance evaluation: a complex network analysis approach;an accurate and flexible early memory system power evaluation approach using a microcomponent method;how to enable software isolation and boost system performance with sub-block erase over 3D flash memory;realizing erase-free SLC flash memory with rewritable programming design;an overview of micron's automata processor;enabling the high level synthesis of data analytics accelerators;and big data analytics on heterogeneous accelerator architectures.

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The RISC-V instruction set architecture optimization and fixed-point math library co-design: Work-in-progress 21

The RISC-V instruction set architecture optimization and fix...

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2021 international conference on hardware/software codesign and system synthesis, codes+isss 2021

作者： Liu, Meng Faculty of Information Technology School of Microelectronics Beijing University of Technology Beijing100124 China

ISBN: (纸本)9781450390767

In the field of IoT, RISC-V as an open-source instruction set shows great application potential. On the one hand, this is due to the low cost brought by the hardware open source trend. On the other hand, the modular instruction set architecture (ISA) design brings agile design ideas, and designers can pay more attention to the collaborative design of key ISA and software libraries. However, by analyzing the underlying mathematical assembly library, we found that the current RISC-V standard instruction set still has room for performance improvement for lightweight control mathematical operations. In this paper, we introduce a set of custom RISC-V ISA designs for fixed-point math libraries and perform performance evaluations to demonstrate the optimization results. © 2021 ACM.

关键词： Open source software

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codes+isss 2021 Message from the Program Chairs

CODES+ISSS 2021 Message from the Program Chairs

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international conference on hardware/software codesign and system synthesis (codes)

Presents the introductory welcome message from the conference proceedings. May include the conference officers' congratulations to all involved with the conference event and publication of the proceedings record.

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Work-in-Progress: A Study of Transistor Degradation in Cyber-Physical system Control Devices

Work-in-Progress: A Study of Transistor Degradation in Cyber...

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international conference on hardware/software codesign and system synthesis (codes)

作者： Spencer Millican SueAnne Griffith Samuel Ginn College of Engineering Auburn University Auburn Alabama USA

ISBN: (纸本)9781665417242

关键词： Degradation Negative bias temperature instability Thermal variables control Aging Cyber-physical systems Transistors

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Work-in-Progress: Improving Security and Maintainability in Modular Embedded systems with hardware Support

Work-in-Progress: Improving Security and Maintainability in ...

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international conference on hardware/software codesign and system synthesis (codes)

作者： Maja Malenko Leandro Batista Ribeiro Marcel Baunach Graz University of Technology Austria

ISBN: (纸本)9781665417242

The current trend of transforming static embedded systems into open platforms (in which several software providers are able to directly load their software) drives the need to design and implement modular embedded software. Additionally, a myriad of embedded devices are expected to operate and provide services for years, or even decades, while remaining correct and secure at all times. Therefore, one of the emerging challenges for highly adaptive embedded computing platforms is to offer dynamic software composition at runtime and internal device housekeeping, which in conjunction improve device maintainability. We propose a hardware/software co-designed technique to improve both security and maintainability in modular embedded systems.

关键词： Embedded computing Runtime Market research hardware Security Embedded software

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The 2019 Embedded systems Week (ESWEEK)

IEEE DESIGN & TEST

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IEEE DESIGN & TEST 2020年第1期37卷 100-101页

作者： Eles, Petru Mitra, Tulika Linkoping Univ Linkoping Sweden Natl Univ Singapore Dept Comp Sci Singapore 117417 Singapore

Embedded systems Week (ESWEEK) is the premier event covering all aspects of hardware and software design for smart, intelligent, and connected computing systems. By bringing together three leading conferences [the international conference on Compilers, Architecture, and synthesis for Embedded systems (CASES), the international conference on hardware/software codesign and system synthesis (codes+isss), and the international conference on Embedded software (EMSOFT)], a special Internet of Medical Things (IoMT) day, a symposium [the international Symposium on Networks-on-Chip (NOCS)], and hottopic workshops and tutorials, ESWEEK presents the attendees with a wide range of topics unveiling state-of-the-art embedded software, embedded architectures, and embedded system designs.

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Work-in-Progress: The RISC-V Instruction Set Architecture Optimization and Fixed-point Math Library Co-design

Work-in-Progress: The RISC-V Instruction Set Architecture Op...

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international conference on hardware/software codesign and system synthesis (codes)

作者： Meng Liu Faculty of Information Technology School of Microelectronics Beijing University of Technology Beijing China

ISBN: (纸本)9781665417242

关键词： Performance evaluation software libraries Costs Instruction sets Computer architecture Market research hardware

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