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Increasing hardware efficiency with multifunction loop accelerators

Increasing hardware efficiency with multifunction loop accel...

引用

codes+isss 2006: 4th international conference on hardware software codesign and system synthesis

作者： Fan, Kevin Kudlur, Manjunath Park, Hyunchul Mahlke, Scott Advanced Computer Architecture Laboratory University of Michigan Ann Arbor MI 48109

ISBN: (纸本)1595933700

To meet the conflicting goals of high-performance low-cost embedded systems, critical application loop nests are commonly executed on specialized hardware accelerators. These loop accelerators are traditionally designed in a single-function manner, wherein each loop nest is implemented as a dedicated hardware block. This paper focuses on hardware sharing across loop nests by creating multifunction loop accelerators, or accelerators capable of executing multiple algorithms. A compiler-based system for automatically synthesizing multifunction loop accelerator architectures from C code is presented. We compare the effectiveness of three architecture synthesis approaches with varying levels of complexity: sum of individual accelerators, union of individual accelerators, and joint accelerator synthesis. Experiments show that multifunction accelerators achieve substantial hardware savings over combinations of single-function designs. In addition, the union approach to multifunction synthesis is shown to be effective at creating low-cost hardware by exploiting hardware sharing, while remaining computationally tractable. © Copyright 2006 ACM.

关键词： Computer hardware

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Automotive electronics system, software, and local area network 06

Automotive electronics system, software, and local area netw...

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codes+isss 2006: 4th international conference on hardware software codesign and system synthesis

作者： Furukawa, Yoshimi Kawamura, Seiji Shibaura Institute of Technology Saitama Japan AutoNetworks Technologies Ltd. Yokkaichi Japan

ISBN: (纸本)1595933700

In this tutorial, an overview of automotive electronic systems and details of the development methodologies are presented. Automobiles were born to enhance human mobile performance. In early development stage, automotive engineers focused to strengthen automobile engine power. Afterwards, automobiles had enough function to drive faster than any animal, but they caused some social problems such as traffic accidents, environmental problems and traffic congestions. Automotive electronic technologies have been developed in order to solve these social *** of electronic technologies on automobile functional developments For the solution to safety, environment and traffic problems, various functions are necessary which could not be completed only by mechanical systems. In this section, roles of automobile electronic systems on countermeasures to the social problems are discussed. Vehicle motion control systems, power-train control systems, navigation systems, and advanced drive assist systems are introduced and automotive functions are defined. Design requirement for automotive electronic systems architecture Electronic systems composed basically of sensors, ECU's (Electronic Control Units), actuators and human interfaces. In early days, each electronic system was designed independently. Today's automobile has various functions which could be completed by multiple electric systems. Therefore, fundamental architecture of integrated electronic systems in an automobile is important to be designed in order to optimize the total function, cost and *** and development procedure of electronic systems and software In vehicle systems and software, required functions and complexity of products are increasing. In this situation, ECU suppliers are working with efficient development methodology to achieve the highest quality. Today most common development processes are still classical V shaped process, module design and C language programming. However, severa

关键词： Automotive engineering

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hardware based frequency/voltage control of voltage frequency island systems

Hardware based frequency/voltage control of voltage frequenc...

引用

codes+isss 2006: 4th international conference on hardware software codesign and system synthesis

作者： Choudhary, Puru Marculescu, Diana Dept. of Electrical and Computer Engineering Carnegie Mellon University 5000 Forbes Ave. Pittsburgh PA 15213

ISBN: (纸本)1595933700

The ability to do fine grain power management via local voltage selection has shown much promise via the use of Voltage/Frequency Islands (VFIs). VFI-based designs combine the advantages of using fine-grain speed and voltage control for reducing energy requirements, while allowing for maintaining performance constraints. We propose a hardware based technique to dynamically change the clock frequencies and potentially voltages of a VFI system driven by the dynamic workload. This technique tries to change the frequency of a synchronous island such that it will have efficient power utilization while satisfying performance constraints. We propose a hardware design that can be used to change the frequencies of various synchronous islands interconnected together by mixed-clock/mixed-voltage FIFO interfaces. Results show up to 65% power savings for the set of benchmarks considered with no loss in throughput. © Copyright 2006 ACM.

关键词： Voltage control

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Streamroller: Automatic synthesis of prescribed throughput accelerator pipelines

Streamroller: Automatic synthesis of prescribed throughput a...

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codes+isss 2006: 4th international conference on hardware software codesign and system synthesis

作者： Kudlur, Manjunath Fan, Kevin Mahlke, Scott Advanced Computer Architecture Laboratory University of Michigan Ann Arbor MI 48109

ISBN: (纸本)1595933700

In this paper, we present a methodology for designing a pipeline of accelerators for an application. The application is modeled using sequential C language with simple stylizations. The synthesis of the accelerator pipeline involves designing loop accelerators for individual kernels, instantiating buffers for arrays used in the application, and hooking up these building blocks to form a pipeline. A compiler-based system automatically synthesizes loop accelerators for individual kernels at varying performance levels. An integer linear program formulation which simultaneously optimizes the cost of loop accelerators and the cost of memory buffers is proposed to compose the loop accelerators to form an accelerator pipeline for the whole application. Cases studies for some applications, including FMRadio and Beamformer, are presented to illustrate our design methodology. Experiments show significant cost savings are achieved through hardware sharing, while achieving the prescribed throughput requirements. © Copyright 2006 ACM.

关键词： Pipeline processing systems

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hardware assisted pre-emptive control flow checking for embedded processors to improve reliability

Hardware assisted pre-emptive control flow checking for embe...

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codes+isss 2006: 4th international conference on hardware software codesign and system synthesis

作者： Ragel, Roshan G. Parameswaran, Sri University of New South Wales National ICT Australia Sydney NSW 2052 Australia

ISBN: (纸本)1595933700

Reliability in embedded processors can be improved by control flow checking and such checking can be conducted using software or hardware. Proposed software-only approaches suffer from significant code size penalties, resulting in poor performance. Proposed hardware-assisted approaches are not scalable and therefore cannot be implemented in real embedded systems. This paper presents a scalable, cost effective and novel fault detection technique, to ensure proper control flow of a program. This technique includes architectural changes to the processor and software modifications. While architectural refinement incorporates additional instructions, the software transformation utilizes these instructions into the program flow. Applications from an embedded systems benchmark suite are used for testing and evaluation. The overheads are compared with the state of the art approach that performs the same error coverage using software-only techniques. Our method has greatly reduced overheads compared to the state of the art. Our approach increased code size by between 3.85-11.2% and reduced performance by just 0.24-1.47% for eight different industry standard applications. The additional hardware (gates) overhead in this approach was just 3.59%. In contrast, the state of the art software-only approach required 50-150% additional code, and reduced performance by 53.5-99.5% when error detection was inserted. © Copyright 2006 ACM.

关键词： Embedded systems

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system-level power-performance trade-offs in bus matrix communication architecture synthesis

System-level power-performance trade-offs in bus matrix comm...

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codes+isss 2006: 4th international conference on hardware software codesign and system synthesis

作者： Pasricha, Sudeep Park, Young-Hwan Kurdahi, Fadi J. Dutt, Nikil Center for Embedded Computer Systems University of California Irvine CA

ISBN: (纸本)1595933700

system-on-chip communication architectures have a significant impact on the performance and power consumption of modern multi-processor system-on-chips (MPSoCs). However, customization of such architectures for an application requires the exploration of a large design space. Thus designers need tools to rapidly explore and evaluate relevant communication architecture configurations exhibiting diverse power and performance characteristics. In this paper we present an automated framework for fast system-level, application-specific, power-performance trade-offs in bus matrix communication architecture synthesis. Our paper makes two specific contributions. First, we develop energy macro-models for system-level exploration of bus matrix communication architectures. Second, we incorporate these macro-models into a bus matrix synthesis flow that enables designers to efficiently explore the power-performance design space of different bus matrix configurations. Experimental results show that our energy macro-models incur less than 5% average absolute error compared to gate-level models. Furthermore, our bus matrix synthesis framework generates a tradeoff space with designs that exhibits an approximately 20% variation in power and 40% variation in performance on an industrial networking MPSoC application, demonstrating the utility of our approach. © Copyright 2006 ACM.

关键词： Communication systems

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Are current ESL tools meeting the requirements of advanced embedded systems

Are current ESL tools meeting the requirements of advanced e...

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codes+isss 2006: 4th international conference on hardware software codesign and system synthesis

作者： Teich, Jürgen University of Erlangen-Nuremberg Germany

ISBN: (纸本)1595933700

Electronic system Level (ESL) tools are becoming more and more important in order to bridge the well-known productivity design gap. This panel brings together specialists from industry and ESL tool houses to discuss whether current ESL tools available are usable and meeting the requirements of the industry. In particular, we would like to know to what degree currently available tools from major ESL tool houses are used for designing what kind of systems in industry, and for what purpose such as analysis, design space exploration, or synthesis, etc. these tools are currently used. Also, we would like to discuss to what degree existing tools can help in reducing design time, and finally, what the industry sees the most challenging features of tools currently not yet available. On the other side, we would like to know the opinion of the ESL tool houses what they see the most important offerings of ESL tools currently available as well as the most challenging points and problems why ESL hasn't really taken off so far. Could this either be an industry issue, a methodology issue, a design issue or a tool issue. © Copyright 2006 ACM.

关键词： Computer aided software engineering

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Fuzzy decision making in embedded system design

Fuzzy decision making in embedded system design

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codes+isss 2006: 4th international conference on hardware software codesign and system synthesis

作者： Di Nuovo, Alessandro G. Palesi, Maurizio Patti, Davide Ascia, Giuseppe Catania, Vincenzo Dipartimento di Ingegneria Informatica e Delle Telecomunicazioni Università Degli Studi di Catania Catania Italy DIIT Università di Catania

ISBN: (纸本)1595933700

The use of Application Specific Instruction-set Processors (ASIP) is a solution to the problem of increasing complexity in embedded systems design. One of the major challenges in ASIP design is Design Space Exploration (DSE), because of the heterogeneity of the objectives and parameters involved. Typically DSE is a multi-objective search problem, where performance, power, area, etc. are the different optimization criteria. The output of a DSE strategy is a set of candidate design solutions called a Pareto-optimal set. Choosing a solution for system implementation from the Pareto-optimal set can be a difficult task, generally because Pareto-optimal sets can be extremely large or even contain an infinite number of solutions. In this paper we propose a methodology to assist the decision-maker in analysis of the solutions to multi-objective problems. By means of fuzzy clustering techniques, it finds the reduced Pareto subset, which best represents all the Pareto solutions. This optimal subset will be used for further and more accurate (but slower) analysis. As a real application example we address the optimization of area, performance, and power of a VLIW-based embedded system. © Copyright 2006 ACM.

关键词： Fuzzy systems

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Generic netlist representation for system and PE level design exploration

Generic netlist representation for system and PE level desig...

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codes+isss 2006: 4th international conference on hardware software codesign and system synthesis

作者： Gorjiara, Bita Reshadi, Mehrdad Chandraiah, Pramod Gajski, Daniel Center for Embedded Computer Systems University of California Irvine

ISBN: (纸本)1595933700

Designer productivity and design predictability are vital factors for successful embedded system design. Shrinking time-to-market and increasing complexity of these systems require more productive design approaches starting from high-level languages such as C. On the other hand, tight constraints of embedded systems require careful design exploration at system level (coarse grained exploration) and at the processing-element (PE) level (fine grained exploration).In this paper we presented GNR, a formal modeling approach, developed to improve productivity of designing systems and processing elements, the same way that traditional ADLs improved productivity for designing processors. The GNR is an order of magnitude shorter than state-of-the-art ADLs with RTL generation capabilities and yet can capture any structural details that affect the implementation quality. Using relatively short GNR description, we explored several designs for implementing an MP3 decoder and achieved 3.25 speedup compared to MicroBlaze processor. We have also developed a web-based interface for our tools, so that users can upload and evaluate new architectures described in GNR. Our toolset and GNR is an intermediate step towards synthesis of TLM to RTL. © Copyright 2006 ACM.

关键词： systems analysis

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Data reuse driven energy-aware MPSoC co-synthesis of memory and communication architecture for streaming applications

Data reuse driven energy-aware MPSoC co-synthesis of memory ...

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codes+isss 2006: 4th international conference on hardware software codesign and system synthesis

作者： Issenin, Ilya Dutt, Nikil University of California Irvine CA 92697

ISBN: (纸本)1595933700

The memory subsystem of a complex multiprocessor systems-on-chip (MPSoC) is an important contributor to the chip power consumption. The selection of memory architecture, as well as of communication architecture, both affect the power efficiency of the design. In this paper we propose a novel approach that enables energy-aware co-synthesis of both memory and communication architecture for streaming applications. As opposed to earlier techniques, we employ a powerful compile-time analysis of memory access behavior that adds flexibility in selecting memory architectures. Additionally, we target TDMA bus-based communication architectures, which not only guarantee performance, but also greatly reduce the design time and allow us to find the energy optimal system configuration. We propose and compare three techniques: an optimal mixed ILP-based co-synthesis technique, a mixed ILP-based traditional two-step synthesis approach where memory and communication synthesis is performed sequentially, and a co-synthesis heuristic that synthesizes energy-efficient hierarchical bus-based communication architectures with guaranteed throughput. Our experimental results on a number of streaming applications show that both the traditional two-step synthesis approach and heuristic result in up to 50% worse power consumption in comparison with proposed co-synthesis approach. However, on some of the streaming benchmarks, our co-synthesis heuristic approach was able to find optimal or near-optimal results in a much shorter time than the MILP co-synthesis approach. © Copyright 2006 ACM.

关键词： Multiprocessing systems

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