检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

566 篇 会议
27 篇 期刊文献

馆藏范围

593 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

291 篇 工学
- 284 篇 计算机科学与技术...
- 248 篇 软件工程
- 66 篇 电子科学与技术（可...
- 30 篇 电气工程
- 29 篇 信息与通信工程
- 26 篇 控制科学与工程
- 8 篇 动力工程及工程热...
- 4 篇 机械工程
- 4 篇 光学工程
- 4 篇 材料科学与工程（可...
- 4 篇 建筑学
- 4 篇 土木工程
- 3 篇 安全科学与工程
- 2 篇 力学（可授工学、理...
- 2 篇 仪器科学与技术
- 1 篇 化学工程与技术
- 1 篇 纺织科学与工程
- 1 篇 轻工技术与工程
- 1 篇 航空宇航科学与技...
71 篇 理学
- 48 篇 数学
- 33 篇 系统科学
- 7 篇 统计学（可授理学、...
- 4 篇 物理学
- 1 篇 生物学
43 篇 管理学
- 35 篇 管理科学与工程(可...
- 13 篇 工商管理
- 10 篇 图书情报与档案管...
4 篇 法学
- 3 篇 社会学
- 1 篇 法学
3 篇 经济学
- 3 篇 应用经济学

主题

122 篇 hardware
73 篇 computer archite...
54 篇 embedded system
50 篇 permission
40 篇 application soft...
38 篇 system-on-a-chip
37 篇 embedded systems
35 篇 energy consumpti...
33 篇 algorithm design...
31 篇 computational mo...
28 篇 space exploratio...
28 篇 software
27 篇 field programmab...
24 篇 runtime
23 篇 system-on-chip
22 篇 timing
22 篇 costs
20 篇 delay
19 篇 registers
19 篇 high level synth...

机构

8 篇 center for embed...
6 篇 school of comput...
6 篇 department of co...
5 篇 school of inform...
5 篇 center for embed...
5 篇 institute for in...
4 篇 university of er...
4 篇 department of el...
4 篇 univ elect sci &...
4 篇 nec laboratories...
4 篇 philips research...
3 篇 integrated signa...
3 篇 department of el...
3 篇 department of co...
3 篇 chongqing univ c...
3 篇 philips research...
3 篇 graz university ...
3 篇 arizona state un...
3 篇 univ calif river...
3 篇 politecn torino ...

作者

7 篇 sri parameswaran
7 篇 ogras umit y.
7 篇 parameswaran sri
7 篇 nikil dutt
7 篇 leupers rainer
6 篇 dutt nikil
6 篇 mitra tulika
5 篇 jiang wei
5 篇 pasricha sudeep
5 篇 rolf ernst
5 篇 robert p. dick
5 篇 jinyu zhan
5 篇 gerstlauer andre...
5 篇 tei-wei kuo
5 篇 wei jiang
5 篇 yuan-hao chang
5 篇 rainer leupers
5 篇 zhan jinyu
5 篇 fummi franco
4 篇 takach andres

语言

593 篇 英文

检索条件"任意字段=2014 International Conference on Hardware/Software Codesign and System Synthesis, CODES ISSS 2014"

共 593 条记录，以下是431-440 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

Yield prediction for architecture exploration in nanometer technology nodes:: a model and case study for memory organizations

Yield prediction for architecture exploration in nanometer t...

引用

international conference on hardware/software codesign and system synthesis (codes)

作者： T. Grabner F. Catthoor M. Miranda P. Roussel A. Papanikolaou IMEC vzw Leuven Belgium

Process variability has a detrimental impact on the performance of memories and other system components, which can lead to parametric yield loss at the system level due to timing violations. Conventional yield models do not allow to accurately analyze this, at least not at the system level. In this paper we propose a technique to estimate this system level yield loss for a number of alternative memory organization implementations. This can aid the designer into making educated trade-offs at the architecture level between energy consumption and parametric timing yield by using memories from different available libraries with different energy/performance characteristics considering the impact of manufacturing variations. The accuracy of this technique is very high, an average error of less than 1% is reported, which enables an early exploration of the available options.

关键词： Predictive models Timing Energy consumption Embedded system Performance loss Yield estimation Manufacturing Power system reliability Real time systems system-level design

来源：评论

学校读者我要写书评

暂无评论

Battery discharge aware energy feasibility analysis

Battery discharge aware energy feasibility analysis

引用

international conference on hardware/software codesign and system synthesis (codes)

作者： Karsten Albers Frank Slomka Henrik Lipskoch University of Oldenburg Germany

It is observed that pulsed discharge currents allow to drain the battery with a higher specific power. Thus they improve the batteries durability and discharge performance. The question is how can the allowed discharge of a battery be modeled. Embedded real-time systems often rely on batteries. For these systems it is necessary to prove both, real-time feasibility and the constraint to not exceed the allowed discharge currents. This paper presents a unified approach for both objectives using the flexible model of event streams, because it allows both to model a complex allowed- discharge curve and the real-time requirements for complex task stimuli. We present the model and the calculation of the allowed and requested discharge curves. Together with the known event- stream based real-time feasibility analysis this allows a unified analysis of both aspects of the system. This work enables the modeling of complex discharge requirements of batteries for real-time systems.

关键词： Batteries Power system modeling Real time systems Power system reliability Embedded system Job shop scheduling Reliability theory Energy consumption Permission Timing

来源：评论

学校读者我要写书评

暂无评论

Increasing the throughput of an adaptive router in network-on-chip (NoC)

Increasing the throughput of an adaptive router in network-o...

引用

international conference on hardware/software codesign and system synthesis (codes)

作者： Nader Bagherzadeh Seung Eun Lee Department of Electrical Engineering and Computer Science University of California Irvine CA USA

In this paper, we propose a simple and efficient mechanism to increase the throughput of an adaptive router in network-on-chip (NoC). One of the most serious disadvantages of fully adaptive wormhole routers is its performance degradation due to the routing decision time. The key idea to overcome this shortcoming is the use of different clocks in a head flit and body flits, because the body flits can be forwarded immediately and the FIFO usually operates faster than route decision logic in an adaptive router. The major contributions of this paper are: 1) a proposal of a simple and efficient mechanism to improve the performance of fully adaptive wormhole routers, 2) a quantitative evaluation of the proposed mechanism showing that the proposed one can support higher throughput than a conventional one, and 3) an evaluation of hardware overhead for the proposed router. In summary, the proposed clock boosting mechanism enhances the throughput of the original adaptive router by increasing the accepted load and decreasing the average latency in the region of effective bandwidth.

关键词： Network-on-a-chip Throughput Adaptive systems Clocks Degradation Routing Logic Proposals hardware Boosting

来源：评论

学校读者我要写书评

暂无评论

A formal approach to robustness maximization of complex heterogeneous embedded systems

A formal approach to robustness maximization of complex hete...

引用

international conference on hardware/software codesign and system synthesis (codes)

作者： Razvan Racu Rolf Ernst Arne Hamann Institute of Computer and Communication Network Engineering Technical University of Braunschweig Germany

Embedded system optimization typically considers objectives such as cost, timing, buffer sizes and power consumption. Robustness criteria, i.e. sensitivity of the system to variations of properties like execution and transmission delays, input data rates, CPU clock rates, etc., has found less attention despite its practical relevance. In this paper we introduce robustness metrics and propose an algorithm considering these metrics in design space exploration and system optimization. The algorithm can optimize for static and for dynamic robustness, the latter including system or designer reactions to property variations. We explain several applications ranging from platform optimization to critical component identification. By means of extensive experiments we show that design space exploration pursuing classical design goals does not necessarily yield robust systems, and that our method leads to systems with significantly higher design robustness.

关键词： Robustness Embedded system Algorithm design and analysis Space exploration Design optimization Cost function Timing Energy consumption Delay Clocks

来源：评论

学校读者我要写书评

暂无评论

hardware assisted pre-emptive control flow checking for embedded processors to improve reliability

Hardware assisted pre-emptive control flow checking for embe...

引用

international conference on hardware/software codesign and system synthesis (codes)

作者： Sri Parameswaran Roshan G. Ragel National ICT Australia University of New South Wales Sydney NSW Australia

Reliability in embedded processors can be improved by control flow checking and such checking can be conducted using software or hardware. Proposed software-only approaches suffer from significant code size penalties, resulting in poor performance. Proposed hardware-assisted approaches are not scalable and therefore cannot be implemented in real embedded systems. This paper presents a scalable, cost effective and novel fault detection technique, to ensure proper control flow of a program. This technique includes architectural changes to the processor and software modifications. While architectural refinement incorporates additional instructions, the software transformation utilizes these instructions into the program flow. Applications from an embedded systems benchmark suite are used for testing and evaluation. The overheads are compared with the state of the art approach that performs the same error coverage using software-only techniques. Our method has greatly reduced overheads compared to the state of the art. Our approach increased code size by between 3.85-11.2% and reduced performance by just 0.24-1.47% for eight different industry standard applications. The additional hardware (gates) overhead in this approach was just 3.59%. In contrast, the state of the art software- only approach required 50-150% additional code, and reduced performance by 53.5-99.5% when error detection was inserted.

关键词： hardware Application software Computer errors Australia software performance Runtime Computer crashes Monitoring Embedded software Embedded system

来源：评论

学校读者我要写书评

暂无评论

Layout aware design of mesh based NoC architectures

Layout aware design of mesh based NoC architectures

引用

international conference on hardware/software codesign and system synthesis (codes)

作者： Karam S. Chatha Krishnan Srinivasan Department of Computer Science and Engineering Arizona State University Tempe AZ USA

Design of system-on-chip (SoC) with regular mesh based network-on-chip (NoC) consists of mapping processing cores to routers, and routing of the traffic traces on the topology such that power consumption is minimized, and performance constraints are satisfied. Technology scaling increases the contribution of the link power to the overall power consumption of the NoC. Since link power consumption is dependent on the length of the link, its contribution cannot be accurately estimated without system-level floorplanning. In this paper, we propose a novel design technique that integrates system- level floorplanning into the NoC design flow. Our technique invokes an existing floorplanner to generate an initial layout of the cores. This is followed by invocation of a novel low complexity algorithm that generates the mesh based NoC architecture with complete information of the floorplan. In comparison to an existing approach, our technique results in lower total power consumption and much lower link power consumption.

关键词： Network-on-a-chip Energy consumption Computer architecture Mesh generation Routing Bandwidth Topology Computer science Design engineering system-on-a-chip

来源：评论

学校读者我要写书评

暂无评论

Bounded arbitration algorithm for QoS-supported on-chip communication

Bounded arbitration algorithm for QoS-supported on-chip comm...

引用

international conference on hardware/software codesign and system synthesis (codes)

作者： Gereon Weiss Joerg Henkel Mohammad Abdullah Al Faruque Computer Science Department University of Karlsruhe Karlsruhe Germany

Time-critical multi-processor systems require guaranteed services in terms of throughput, bandwidth etc. in order to comply to hard real-time constraints. However, guaranteed-service schemes suffer from low resource utilization. To the best of our knowledge, we are presenting the first approach for on-chip communication that provides a high resource utilization under a transaction-specific, flexible (i.e. different classifications on data exchange) communication scheme. It does provide tight time-related guarantees. Hence, we are presenting our bounded arbitration scheme considering lower and upper bounds for each type of transaction level. We demonstrate its advantages by means of a complete MPEG4 decoder case study and achieve under these constraints a bandwidth utilization of up to 100%, on an average 97% with a guaranteed (100%) bandwidth.

关键词： Quality of service Network-on-a-chip Bandwidth Embedded system system-on-a-chip Time factors Resource management Routing Throughput Real time systems

来源：评论

学校读者我要写书评

暂无评论

Application-specific workload shaping in multimedia-enabled personal mobile devices

Application-specific workload shaping in multimedia-enabled ...

引用

international conference on hardware/software codesign and system synthesis (codes)

作者： Samarjit Chakraborty Balaji Raman Department of Computer Science National University of Singapore Singapore

Today, most personal mobile devices (e.g. cell phones and PDAs) are multimedia-enabled and support a variety of concurrently running applications such as audio/video players, word processors and Web browsers. Media-processing applications are often computationally expensive and most of these devices typically have 100 - 400 MHz processors. As a result, the user-perceived application response times are often poor when multiple applications are concurrently fired. In this paper we show that by using application-specific dynamic buffering techniques, the workload of these applications can be suitably "shaped" to fit the available processor bandwidth. Our techniques are analogous to traffic shaping which is widely used in communication networks to optimally utilize network bandwidth. Such shaping techniques have recently attracted a lot of attention in the context of embedded systems design (e.g. for dynamic voltage scaling). However, they have not been exploited for enhanced schedulability of multiple applications, as we do in this paper.

关键词： Bandwidth Cellular phones Personal digital assistants Computer applications Delay Telecommunication traffic Communication networks Context Embedded system Dynamic voltage scaling

来源：评论

学校读者我要写书评

暂无评论

Automatic generation of transaction level models for rapid design space exploration

Automatic generation of transaction level models for rapid d...

引用

international conference on hardware/software codesign and system synthesis (codes)

作者： Junyu Peng Andreas Gerstlauer Daniel D. Gajski Rainer Domer Dongwan Shin Center for Embedded Computer Systems University of California Irvine CA USA

Transaction-level modeling has been touted to improve simulation performance and modeling efficiency for early design space exploration. But no tools are available to generate such transaction-level models from abstract input descriptions. Designers have to write such models manually, which is a tedious and error-prone task, and one of bottlenecks in improving designer's productivity. In this paper, we propose a method to generate transaction-level models from virtual architecture models where components communicate via abstract message-passing channels. We have applied our approach to a set of industrial-strength examples with a wide range of target architectures. Experimental results show that significant productivity gains can be achieved, demonstrating the effectiveness and benefits of our approach for rapid, early exploration of communication design space.

关键词： Space exploration Computational modeling Productivity system-on-a-chip Permission Concrete Embedded computing Computer simulation Design automation system-level design

来源：评论

学校读者我要写书评

暂无评论

system-level power-performance trade-offs in bus matrix communication architecture synthesis

System-level power-performance trade-offs in bus matrix comm...

引用

international conference on hardware/software codesign and system synthesis (codes)

作者： Young-Hwan Park Fadi J. Kurdahi Nikil Dutt Sudeep Pasricha Center for Embedded Computer Systems University of California Irvine CA USA

system-on-chip communication architectures have a significant impact on the performance and power consumption of modern multiprocessor system-on-chips (MPSoCs). However, customization of such architectures for an application requires the exploration of a large design space. Thus designers need tools to rapidly explore and evaluate relevant communication architecture configurations exhibiting diverse power and performance characteristics. In this paper we present an automated framework for fast system-level, application-specific, power- performance trade-offs in bus matrix communication architecture synthesis. Our paper makes two specific contributions. First, we develop energy macro-models for system-level exploration of bus matrix communication architectures. Second, we incorporate these macro- models into a bus matrix synthesis flow that enables designers to efficiently explore the power-performance design space of different bus matrix configurations. Experimental results show that our energy macro- models incur less than 5% average absolute error compared to gate-level models. Furthermore, our bus matrix synthesis framework generates a tradeoff space with designs that exhibits an approximately 20% variation in power and 40% variation in performance on an industrial networking MPSoC application, demonstrating the utility of our approach.

关键词： Energy consumption Computer architecture system-on-a-chip Space exploration Bandwidth Integrated circuit synthesis Network-on-a-chip Embedded computing Multiprocessing systems Application software

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共60页 << < 40 41 42 43 44 45 46 47 48 49 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：