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hardware and software architectures for the Cell processor 05

Hardware and software architectures for the Cell processor

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3rd IEEE/ACM/IFIP international conference on hardware/software codesign and systems synthesis codes+isss 2005

作者： Hofstee, Peter Day, Michael IBM Systems and Technology Group Austin TX United States

ISBN: (纸本)1595931619

The Cell processor is a first instance of a new family of processors intended for the broadband era. The processors will find early use in game systems (PlayStation3™), a variety of other consumer electronics applications, a wide variety of embedded applications, and various forms of computational accelerators. Cell is a non-homogeneous multi-core processor, with one POWER processor core (two threads) dedicated to the operating system and other control functions, and eight synergistic processors optimized for compute-intensive applications. Cell addresses two of the main limiters to microprocessor performance: increased memory latency, and performance limitations induced by system power limits. Memory latency is addressed by introducing another software-managed level of private "local" memory, in between the private registers and shared system memory. Data is transferred between this local memory and shared memory with asynchronous cache coherent DMA commands, and synergistic processor load and store commands access the local store only. This organization of memory makes it possible for the Cell processor to have over 100 memory transactions in flight at the same time, more than enough to cover memory latency. Power limitations are addressed by two main mechanisms;a non-homogeneous multi-core organization, and an ultra high-frequency design that allows the chip to be operated at 3.2GHz at low voltage. The Cell processor supports many of today's programming models by introducing the concept of heterogeneous tasks or threads. Both Power processor and SPE based threads can be managed by the operating system and effectively utilized by applications starting with the relatively straightforward function offload model to the more complex single source heterogeneous parallel programming model. Cell achieves between one and two orders of magnitude of performance advantage over conventional single-core processors on compute-intensive (32-bit) applications, by permitting progr

关键词： Computer architecture

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Enhancing security through hardware-assisted run-time validation of program data properties 05

Enhancing security through hardware-assisted run-time valida...

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3rd IEEE/ACM/IFIP international conference on hardware/software codesign and systems synthesis codes+isss 2005

作者： Arora, Divya Raghunathan, Anand Ravi, Srivaths Jha, Niraj K. Dept. of Electrical Engineering Princeton University Princeton NJ 08544 United States NEC Laboratories America Princeton NJ 08540 United States

ISBN: (纸本)1595931619

The growing number of information security breaches in electronic and computing systems calls for new design paradigms that consider security as a primary design objective. This is particularly relevant in the embedded domain, where the security solution should be customized to the needs of the target system, while considering other design objectives such as cost, performance, and power. Due to the increasing complexity and shrinking design cycles of embedded software, most embedded systems present a host of software vulnerabilities that can be exploited by security attacks. Many attacks are initiated by causing a violation in the properties of data (e.g., integrity, privacy, access control rules, etc.) associated with a "trusted" program that is executing on the system, leading to a range of undesirable effects. In this work, we develop a general framework that provides security assurance against a wide class of security attacks. Our work is based on the observation that a program's permissible behavior with respect to data accesses can be characterized by certain properties. We present a hardware/software approach wherein such properties can be encoded as data attributes and enforced as security policies during program execution. These policies may be application-specific (e.g., access control for certain data structures), compiler-generated (e.g., enforcing that variables are accessed only within their scope), or universally applicable to all programs (e.g., disallowing writes to unallocated memory). We show how an embedded system architecture can support, such policies by (i) enhancing the memory hierarchy to represent the attributes of each datum as security tags that are linked to it through its lifetime, and (ii) adding a configurable hardware checker that interprets the semantics of the tags and enforces the desired security policies. We evaluated the effectiveness of the proposed architecture in enforcing various security policies for several embedded bench

关键词： Data reduction

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FIDES: An advanced chip multiprocessor platform for secure next generation mobile terminals

FIDES: An advanced chip multiprocessor platform for secure n...

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3rd IEEE/ACM/IFIP international conference on hardware/software codesign and systems synthesis codes+isss 2005

作者： Inoue, Hiroaki Ikeno, Akihisa Kondo, Masaki Sakai, Junji Edahiro, Masato System Devices Research Laboratories NEC Corporation 1120 Shimokuzawa Sagamihara Kanagawa 229-1198 Japan NEC Informatec Systems Ltd. 3-2-1 Sakado Kawasaki Kanagawa 213-0012 Japan

ISBN: (纸本)1595931619

We propose a secure platform on a chip multiprocessor, known as FIDES, in order to enable next generation mobile terminals to execute downloaded native applications for Linux. Its most important feature is the higher security based on multi-grained separation mechanisms: coarse-grained processor-level separation of the basic-function domain from other domains for such downloaded applications, medium-grained OS-level separation, and fine-grained process-level separation within SELinux. Four new technologies, which include three enhancements to SELinux, support the FIDES platform: 1) bus filter logic for processor-level separation can be implemented as a small logic, 2) XIP kernels for memory-efficient OS-level separation can reduce memory requirements by 182%, 3) policy separation for enhanced process-level separation can apply policies 2.1 times faster at system bootup, and 4) dynamic access control can provide secure Inter-Domain Communications (IDCs) with an overhead of only 4% for IDC system calls. We implemented SELinuxes on an ARM-based multiprocessor. Therefore, the best-suited platform to secure next generation mobile terminals is the FIDES platform, which can provide higher security as well as higher performance and lower power consumption on chip multiprocessors leading the current technology trend of microprocessors. Copyright 2005 ACM.

关键词： Microprocessor chips

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Developing design tools for biological and biomedical applications of micro- and nano-technology

Developing design tools for biological and biomedical applic...

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international conference on hardware/software codesign and system synthesis (codes)

作者： Jacob White Electrical Engineering and Computer Science Research Laboratory of Electronics Massachusetts Institute of Technology Cambridge MA USA

This short paper, an update of [75], is intended to provide a brief summary and extensive references on biological applications for micro- and nano-machining, as well as the computer-aided design challenges generated ... 详细信息

关键词： Nanobioscience Design automation Nanoscale devices Micromechanical devices Nanoelectromechanical systems Application software Electrostatics Biology Gene expression Prototypes

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The challenges of embedded system design

The challenges of embedded system design

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international conference on hardware/software codesign and system synthesis (codes)

作者： Mike Muller ARM Inc.

As complexity grows the importance of system level exploration, design, verification and debug becomes inescapable. However while there has been great progress in process technology, tools and methodologies resulting in ever more sophisticated platforms some of the critical design parameters have been moving in the wrong direction. Power is becoming a critical challenge that will require new solutions for both design and manufacturing if the roller coaster ride is to continue.

关键词： Embedded system Manufacturing Computer architecture Computer science Board of Directors Cities and towns

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A core flight software system

A core flight software system

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international conference on hardware/software codesign and system synthesis (codes)

作者： Jonathan Wilmot Flight Software Branch Goddard Space Flight Center NASA Greenbelt MD USA

No two flight missions are alike, hence, development and on-orbit software costs are high. software portability and adaptability across hardware platforms and operating systems has been minimal at best. Standard interfaces across applications and/or common applications are almost non-existent. To reduce flight software costs, these issues must be addressed. This presentation describes how the Flight software Branch at Goddard Space Flight Center has architected a solution to these problems.

关键词： software systems Application software Operating systems Computer architecture Costs hardware Space vehicles Embedded software software architecture Plugs

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Implementation of dynamic streaming Applications on heterogeneous multi-Processor architectures

Implementation of dynamic streaming Applications on heteroge...

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international conference on hardware/software codesign and system synthesis (codes)

作者： Pieter Van Der Wolf Jeffrey Kang Tomas Henriksson Philips Research Eindhoven The Netherlands

system design based on static task graphs does not match well with modern consumer electronic devices with dynamic stream processing *** propose the TTL API for task graph reconfiguration services,which can be used to describe the dynamic behaviour of *** demonstrate the efficient implementation of the TTL API on a heterogeneous multi-processor *** is possible to design dynamic streaming applications with reusable reconfiguration-aware tasks and we argue that the TTL API serves as a good starting point for standardization.

关键词： Topology Computer architecture Consumer electronics Standardization TV Decoding Streaming media Embedded system system-level design Application software

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Energy conscious online architecture adaptation for varying latency constraints in sensor network applications

Energy conscious online architecture adaptation for varying ...

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international conference on hardware/software codesign and system synthesis (codes)

作者： Alex Doboli Sankalp Kallakuri ECE Department Stony Brook University New York NY USA

Sensor network applications face continuously changing environments, which impose varying processing loads on the sensor node. This paper presents an online control method which adapts the architecture to minimize energy consumption while satisfying varying latency constraints. The method predicts processing load requirements over a finite time window and accordingly adapts the architecture. The behaviour of the hardware modules over time has been approximated with a Continuous Time Markov Process. Adaptive image processing for vehicle tracking was used as a case study for this approach.

关键词： Delay Computer architecture Vehicles Energy consumption hardware Markov processes Image processing Application software Image sampling Computer networks

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An integer linear programming approach for identifying instruction-set extensions

An integer linear programming approach for identifying instr...

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international conference on hardware/software codesign and system synthesis (codes)

作者： Can Ozturan Gunhan Dundar Kubilay Atasu Department of computer Engineering Bogazici University Turkey Department of Electrical and Electronics Engineering Bogazici University Turkey

This paper presents an Integer Linear Programming (ILP) approach to the instruction-set extension identification problem. An algorithm that iteratively generates and solves a set of ILP problems in order to generate a set of templates is proposed. A selection algorithm that ranks the generated templates based on isomorphism testing and potential evaluation is described. A Trimaran based framework is used to evaluate the quality of the instructions generated by the technique. Speed-up results of up to 7.5 are observed.

关键词： Integer linear programming Computer aided instruction Computer architecture Application specific processors Delay Embedded computing Iterative algorithms Embedded system Application software Costs

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system-level design automation tools for digital microfluidic biochips

System-level design automation tools for digital microfluidi...

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international conference on hardware/software codesign and system synthesis (codes)

作者： Fei Su Krishnendu Chakrabarty Department of Electrical and Computer Engineering Duke University Durham NC USA

Biochips based on digital microfluidics offer a powerful platform for massively parallel biochemical analysis such as clinical diagnosis and DNA sequencing. Current full-custom design techniques for digital microfluidic biochips do not scale well for increasing levels of system integration. Analogous to classical VLSI synthesis, a top-down system-level design automation approach can shorten the biochip design cycle and reduce human effort. We present here an overview of a system-level design methodology that includes architectural synthesis and physical design. The proposed design automation approach is expected to relieve biochip users from the burden of manual optimization of bioassays, time-consuming hardware design, and costly testing and maintenance procedures.

关键词： system-level design Design automation Microfluidics Biochemical analysis Clinical diagnosis DNA Very large scale integration Humans Design optimization hardware

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