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Future processors: flexible and modular

Future processors: flexible and modular

引用

international conference on hardware/software codesign and system synthesis (codes)

作者： Jeff Welser Charlie Johnson IBM Rochester MN USA IBM San Jose CA USA

The ability to continue increasing processor frequency and single thread performance is being severely limited by exponential increases in leakage and active power. To continue to improve system performance, future designs will rely on increasing numbers of smaller, more power efficient cores and special purpose accelerators integrated on a chip. In this paper, we describe how these trends are leading to more modular, SoC-like designs for future processor chips, which can still achieve very high throughput performance while using simplified components and a cost efficient design methodology.

关键词： Frequency Yarn Microprocessors Circuits Pipeline processing Logic devices Latches Transistors Logic design system performance

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Automated data cache placement for embedded VLIW ASIPs

Automated data cache placement for embedded VLIW ASIPs

引用

international conference on hardware/software codesign and system synthesis (codes)

作者： Richard Taylor Barry O'Rourke George Bruce Japheth Hossell Paul Morgan Institute for System Level Integration Livingston UK Critical Blue Limited SMC Edinburgh UK

Memory bandwidth issues present a formidable bottleneck to accelerating embedded applications, particularly data bandwidth for multiple-issue VLIW processors. Providing an efficient ASIP data cache solution requires that the cache design be tailored to the target application. Multiple caches or caches with multiple ports allow simultaneous parallel access to data, alleviating the bandwidth problem if data is placed effectively. We present a solution that greatly simplifies the creation of targeted caches and automates the process of explicitly allocating individual memory access to caches and banks. The effectiveness of our solution is demonstrated with experimental results.

关键词： VLIW Application specific processors Bandwidth hardware Computer architecture Application software Performance analysis Algorithm design and analysis Permission Acceleration

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A multicast inter-task communication protocol for embedded multiprocessor systems

A multicast inter-task communication protocol for embedded m...

引用

international conference on hardware/software codesign and system synthesis (codes)

作者： Wido Kruijtzer Gustavo Marrero Antonio Nunez Tomas Bautista Victor Reyes IUMA Institute for Applied Microelectronics University of Las Palmas Las Palmas Spain Philips Research Laboratories Eindhoven Netherlands

Recently, a new programming model and platform interface for MPSoC design and integration called TTL (Task Transaction Level) has been developed and advocated as a standard. In this paper, a specific implementation of the TTL interface named ITCP (Inter-Task Communication Protocol) is presented. ITCP is well suited for both hardware and software implementations and supports features such as multitasking and multicast communication. A configurable systemC model of the ITCP protocol and its integration in a system-level design methodology is disclosed in this work. Moreover, details of a multi-task ITCP software shell implementation for an ARM9 with eCos RTOS are also given in the paper.

关键词： Multicast protocols Multiprocessing systems hardware Application software system-level design Object oriented modeling Standards development Multitasking Multicast communication Parallel programming

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Automatic network generation for system-on-chip communication design

Automatic network generation for system-on-chip communicatio...

引用

international conference on hardware/software codesign and system synthesis (codes)

作者： Andreas Gerstlauer Daniel D. Gajski Rainer Domer Dongwan Shin Center for Embedded Computer Systems University of California Irvine CA USA

With growing system complexities, system-level communication design is becoming increasingly important and advanced, network-oriented communication architectures become necessary. In this paper, we extend previous work on automatic communication refinement to support non-traditional, network-oriented architectures beyond a single bus. From an abstract description of the desired communication channels, the refinement tools automatically generate executable models and implementations of the system communication at various levels of abstraction. Experimental results show that significant productivity gains can be achieved, demonstrating the effectiveness of the approach for rapid, early communication design space exploration.

关键词： system-on-a-chip Network topology system-level design Permission Message passing Computer networks Embedded computing Computational modeling Computer simulation Time to market

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Iterational retiming: maximize iteration-level parallelism for nested loops

Iterational retiming: maximize iteration-level parallelism f...

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international conference on hardware/software codesign and system synthesis (codes)

作者： Zili Shao Edwin H.-m. Sha Meilin Liu Chun Xue Department of Computer Science University of Texas Dallas USA

Nested loops are the most critical sections in many scientific and Digital Signal Processing (DSP)*** is important to study effective and efficient transformation techniques to increase parallelism for nested *** this paper, we propose a novel technique,iterational retiming,that can satisfy any given timing constraint by achieving full parallelism for iterations in a partition. Theorems and efficient algorithms are proposed for iterational retiming. The experimental results show that iterational retiming is a promising technique for parallel embedded *** can achieve 87% improvement over software pipelining and 88%improvement over loop unfolding on average.

关键词： Parallel processing Application software Timing Optimal scheduling Digital signal processing Partitioning algorithms Embedded system Application specific integrated circuits Permission Computer science

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Key research problems in NoC design: a holistic perspective

Key research problems in NoC design: a holistic perspective

引用

international conference on hardware/software codesign and system synthesis (codes)

作者： Radu Marculescu Jingcao Hu Umit Y. Ogras Department of Electrical and Computer Engineering Carnegie Mellon University Pittsburgh PA USA

Networks-on-Chip (NoCs) have been recently proposed as a promising solution to complex on-chip communication problems. The lack of an unified representation of applications and architectures makes NoC problem formulation and classification both difficult and obscure. To remedy this situation, we provide a general description for NoC architectures and applications and then enumerate several outstanding research problems (denoted by P1-P8) organized under three topics: communication infrastructure synthesis, communication paradigm selection, and application mapping optimization. Far from being exhaustive, the discussed problems are deemed essential for future NoC research.

关键词： Network-on-a-chip Application software Design automation Design methodology Permission Computer architecture Design optimization Computer applications Algorithm design and analysis Multiprocessor interconnection networks

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Rappit: framework for synthesis of host-assisted scripting engines for adaptive embedded systems

Rappit: framework for synthesis of host-assisted scripting e...

引用

international conference on hardware/software codesign and system synthesis (codes)

作者： Pai H. Chou Qiang Xie Jiwon Hahn Center for Embedded Computer Systems University of California Irvine USA

Scripting is a powerful, high-level, cross-platform, dynamic, easy way of composing software modules as black boxes. Unfortunately, the high runtime overhead has prevented scripting from being widely adopted in embedded applications. This work proposes to overcome these obstacles by synthesizing light-weight, host-assisted scripting engines for embedded systems. The result is dramatically shortened development cycle due to the much higher-level abstraction, interactive access and dynamic reconfigurability, robust in-field software upgradability, and compact code size. This framework has been successfully applied to ultra low-power sensor nodes with under 10KB of program memory to high-performance platforms with fast Ethernet.

关键词： Engines Adaptive systems Embedded system Embedded software Runtime Application software Embedded computing Robustness Ethernet networks Permission

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Comparing the size of .NET applications with native code

Comparing the size of .NET applications with native code

引用

international conference on hardware/software codesign and system synthesis (codes)

作者： Erven Rohou Roberto Costa STMicroelectronics Manno Switzerland

Byte-code based languages are slowly becoming adopted in embedded domains because of improved security and portability. Another potential reason for their adoption is the reputation for smaller code size than native. This is critical in contexts in which a small memory footprint is crucial to reduce production costs. This paper compares the code size of applications compiled for .NET framework with the same natively compiled for various processors. The paper shows that the assumption of an impressive code size reduction is not reachable and it suggests that the adoption of such languages in embedded contexts be justified by additional arguments. The paper also studies the reasons for this and it compares with the compression ratios achievable for various applications through alternative techniques.

关键词： Java Computer languages Libraries ISO standards Security Runtime environment Application software Computer aided manufacturing Permission Yarn

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Enabling unrestricted automated synthesis of portable hardware accelerators for virtual machines

Enabling unrestricted automated synthesis of portable hardwa...

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international conference on hardware/software codesign and system synthesis (codes)

作者： Laura Pozzi Paolo Ienne Christophe Dubach Miljan VuletiC School of Computer and Communication Sciences Ecole Polytechnique Fédérale de Lausanne Lausanne Switzerland

The performance of virtual machines (e.g., Java Virtual Machines---JVMs) can be significantly improved when critical code sections (e.g., Java bytecode methods) are migrated from software to reconfigurable hardware. In contrast to the compile-once-run-anywhere concept of virtual machines, reconfigurable applications lack portability and transparent SW/HW interfacing: applicability of accelerated hardware solutions is often limited to a single platform. In this work, we apply a virtualisation layer that provides portable and seamless integration of hardware and software components to a Java Virtual Machine platform, making it capable of accelerating any Java bytecode method by using platform-independent hardware accelerators. The virtualisation layer not only improves portability of accelerated Java bytecode applications, but also supports runtime optimisations and enables unrestricted automated synthesis of arbitrary Java bytecode to hardware. To show the advantages and measure the limited overheads of our approach, we run several accelerated applications (handwritten and synthesised) on a real embedded platform. We also show our synthesis flow and discuss its advanced features fostered by the virtualisation layer.

关键词： hardware Virtual machining Application software Java Acceleration Field programmable gate arrays software performance Permission Microprocessors Programmable logic arrays

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Enhanced code density of embedded CISC processors with echo technology

Enhanced code density of embedded CISC processors with echo ...

引用

international conference on hardware/software codesign and system synthesis (codes)

作者： Mauricio Breternitz Herbert Hum Ramesh Peri Jay Pickett Youfeng Wu INTEL Research Laboratory Santa Clara CA USA Low Power Microprocessor Laboratory INTEL Research Laboratory Santa Clara CA USA Compiler Laboratory INTEL Research Laboratory Santa Clara CA USA

Code density is an important issue in memory constrained systems. Some RISC processor, e.g. the THUMB extension in the ARM processor, supports aggressive code size reduction even at the cost of significant performance loss. In this paper, we develop an algorithm that utilizes a set of novel variable length Echo instructions and evaluate its effectiveness for IA32 binaries. Our experiments show that IA32 processor equipped with Echo instructions is capable of achieving a similar code density as the THUMB extension in the ARM instruction set with significantly lower performance penalty.

关键词： Thumb Performance loss Reduced instruction set computing Program processors Costs Design optimization Optimizing compilers Embedded system Permission Microprocessors

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