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A power estimation methodology for systemC transaction level models

A power estimation methodology for systemC transaction level...

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international conference on hardware/software codesign and system synthesis (codes)

作者： Vijay Narayanan Ing-chao Lin Nagu Dhanwada IBM Electronic Design Automation Systems and Technology Group Hopewell Junction NY USA Department of Computer Science Pennsylvania State University University Park PA USA

Majority of existing works on system level power estimation have focused on the processor, while there are very few that address power consumption of peripherals in a SoC. With the presence of complex cores in current day embedded system-on-chip devices, the problem of complete system level power estimation is gaining significance. Transaction level models for SoCs are gaining increasing attention with emerging architectural modeling standards like systemC. In this paper we present a methodology for performing system power estimation for different scenarios or applications being executed on these transaction level models. We describe techniques and a setup for transaction level power characterization, and an approach to augment systemC transaction level models to perform transaction level power estimation. We also present experimental results to validate the accuracy and speed of our approach.

关键词： Power system modeling Integrated circuit modeling Energy consumption Frequency Bandwidth Embedded software Computer architecture State estimation Computer science system-on-a-chip

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Dynamic phase analysis for cycle-close trace generation

Dynamic phase analysis for cycle-close trace generation

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international conference on hardware/software codesign and system synthesis (codes)

作者： Rajesh Gupta Brad Calder Jeremy Lau Cristiano Pereira Department of Computer Science and Engineering University of California San Diego USA

For embedded system development, several companies provide cross-platform development tools to aid in debugging, prototyping and optimization of programs. These are full system emulation systems that can emulate the final binary to be run on the real board, its operating system and devices. Many of these emulation systems do not provide cycle level information due to the time consuming nature of cycle accurate *** this paper we propose a method to provide Cycle-Close Traces of cycle-level statistics for the complete execution of the program in orders of magnitude less time than performing full cycle accurate simulation, with an average error of 3.2%. Our approach uses dynamic phase analysis to generate targeted cycle-close simulation samples. Detailed simulation results for these samples are used to produce fast cycle-close traces during a program's execution, so the user can also watch, pause and debug the currently executing code and its corresponding architecture performance characteristics at any point during execution.

关键词： Analytical models Emulation software debugging software performance Embedded system Operating systems hardware Permission Computer science Design engineering

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Power-smart system-on-chip architecture for embedded cryptosystems

Power-smart system-on-chip architecture for embedded cryptos...

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international conference on hardware/software codesign and system synthesis (codes)

作者： H. Vahedi S. Gregori Y. Zhanrong R. Muresan School of Engineering University of Guelph Guelph Canada

In embedded cryptosystems, sensitive information can leak via timing, power, and electromagnetic channels. We introduce a novel power-smart system-on-chip architecture that provides support for masking these channels by controlling, in real-time, the power and the current consumption of a system to predefined programmable values. The main components of the architecture are a processor core, a current sensor module, a dynamically controlled power supply module, a clock frequency control module, and a current injection module. Real-time current measurements and power-aware voltage control are used in closed loop architecture to regulate and minimize the total power consumption of the system. Simulation results show that the current consumption of the system can be regulated to a reference level with reduced power-to-security trade off (power overhead less than 12% of the total power).

关键词： system-on-a-chip Cryptography Real time systems Timing Control systems Power supplies Clocks Frequency control Current measurement Voltage control

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FlexPath NP: a network processor concept with application-driven flexible processing paths

FlexPath NP: a network processor concept with application-dr...

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international conference on hardware/software codesign and system synthesis (codes)

作者： Andreas Herkersdorf Thomas Wild Rainer Ohlendorf Munich University of Technology Munich Germany

In this paper, we present a new architectural concept for network processors called FlexPath NP. The central idea behind FlexPath NP is to systematically map network processor (NP) application sub-functions onto both SW programmable processor (CPU) resources and (re-)configurable HW building blocks, such that different packet flows are forwarded via different, optimized processing paths through the NP. Packets with well understood, relatively simple processing requirements may even bypass the central CPU complex (AutoRoute). In consequence, CPU processing resources are more effectively used and the overall NP performance and throughput are improved compared to conventional NP architectures. We present analytical performance estimations to quantify the performance advantage of FlexPath (expressed as available CPU instructions for each packet traversing the CPUs) and introduce a platform-based system on Programmable Chip (SoPC) based architecture which implements the FlexPath NP concept.

关键词： hardware Throughput Very large scale integration Virtual private networks DSL Computer architecture Permission Performance analysis Coprocessors Network interfaces

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A system-level methodology for fully compensating process variability impact of memory organizations in periodic applications

A system-level methodology for fully compensating process va...

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international conference on hardware/software codesign and system synthesis (codes)

作者： H. Wang M. Miranda F. Lobmaier F. Catthoor A. Papanikolaou IMEC vzw Leuven Belgium Katholieke Universiteit Leuven Leuven Belgium

Process variability is an emerging problem that is becoming worse with each new technology node. Its impact on the performance and energy of memory organizations is severe and degrades the system-level parametric yield. In this paper we propose a broadly applicable system-level technique that can guarantee parametric yield on the memory organization and which minimizes the energy overhead associated to variability in the conventional design process. It is based on offering configuration capabilities at the memory-level and exploiting them at the system-level. This technique can decrease by up to a factor of 5 the energy overhead that is introduced by state-of-the-art process variability compensation techniques, including statistical timing analysis. In this way we obtain results close to the ideal nominal design again.

关键词： Timing Energy consumption Degradation Delay Process design Integrated circuit yield Robustness Runtime Permission Control systems

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hardware/software partitioning of software binaries: a case study of H.264 decode

Hardware/software partitioning of software binaries: a case ...

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international conference on hardware/software codesign and system synthesis (codes)

作者： Gordon McGregor Brian Einloth Frank Vahid Greg Stitt Department of Computer Science and Engineering University of California Riverside USA Center for Embedded Computer Systems University of California Irvine USA Freescale Semiconductor Inc. USA

We describe results of a case study whose intent was to determine whether new techniques for hardware/software partitioning of an application's binary are competitive with partitioning at the C source code level. While such competitiveness has been shown previously for standard benchmark suites involving smaller or unoptimized applications, the case study instead focuses on a complete 16,000-line highly-optimized commercial-grade application, namely an H.264 video decoder. The several month study revealed that binary partitioning was indeed competitive, achieving nearly identical 2.5x speedups as source level partitioning, compared to a standard microprocessor. Furthermore, the study revealed that several simple C-level coding modifications, including pass by value-return, function specialization, algorithmic specialization, hardware-targeted reimplementation, global array elimination, hoisting and sinking of error code, and conversion to explicit control flow, could lead to improved application speedups approaching 7x for both source level and binary level partitioning.

关键词： hardware Decoding Microprocessors Embedded software Field programmable gate arrays Application software software performance Kernel Partitioning algorithms Embedded system

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Service dependency graph: an efficient model for hardware/software interfaces modeling and generation for SoC design

Service dependency graph: an efficient model for hardware/so...

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international conference on hardware/software codesign and system synthesis (codes)

作者： Ahmed Amine Jerraya Frederic Rousseau Aimen Bouchhima Mohamed-wassim Youssef Arnaud Grasset Wander Cesario Lobna Kriaa Adriano Sarmento SLS Group TIMA Laboratory Grenoble France

Complex systems-on-chip are designed by interconnecting pre-designed hardware (HW) and software (SW) components. During the design cycle, a global model of the SoC may be composed of HW and SW models at different abstraction levels. Designing HW/SW interfaces to interconnect SoC components is a source of design bottlenecks. This paper describes a service-based model enabling systematic design and co-simulation of HW/SW interfaces for SoC design. This model, called Service dependency graph (SDG) allows modeling of complex and application-specific interfaces. We present also a model generator that can automatically build HW/SW interfaces based on service and resource requirements described by the SDG. This approach has been applied successfully on the design of an MPEG-4 encoder. Additionally the SDG seems to be an excellent intermediate representation for the design automation of HW/SW interfaces.

关键词： hardware Middleware Costs Design automation Time to market Laboratories Laser sintering MPEG 4 Standard Computer aided instruction Computer interfaces

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A unified approach to constrained mapping and routing on network-on-chip architectures

A unified approach to constrained mapping and routing on net...

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international conference on hardware/software codesign and system synthesis (codes)

作者： Kees Goossens Andrei Radulescu Andreas Hansson Department of Information Technology Lund University Lund Sweden Philips Research Laboratories Eindhoven Netherlands

One of the key steps in Network-on-Chip (NoC) based design is spatial mapping of cores and routing of the communication between those cores. Known solutions to the mapping and routing problem first map cores onto a topology and then route communication, using separated and possibly conflicting objective functions. In this paper we present a unified single-objective algorithm, called Unified MApping, Routing and Slot allocation (UMARS). As the main contribution we show how to couple path selection, mapping of cores and TDMA time-slot allocation such that the network required to meet the constraints of the application is minimized. The time-complexity of UMARS is low and experimental results indicate a run-time only 20% higher than that of path selection alone. We apply the algorithm to an MPEG decoder system-on-Chip (SoC), reducing area by 33%, power by 35% and worst-case latency by a factor four over a traditional multi-step approach.

关键词： Routing Network-on-a-chip Computer architecture Laboratories Network topology Runtime Decoding system-on-a-chip Delay Measurement

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The design of a smart imaging core for automotive and consumer applications: a case study

The design of a smart imaging core for automotive and consum...

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international conference on hardware/software codesign and system synthesis (codes)

作者： Ghiath Alkadi Victor Reyes Bruno Steux Jorn Jochalsky Thomas Hinz Winfried Gehrke Wido Kruijtzer Philips Research Eindhoven The Netherlands Philips Semiconductors Hamburg Germany University of Las Palmas GC Spain University of Hannover Germany École des Mines de Paris France

This paper describes the design of a low-cost, low-power smart imaging core that can be embedded in cameras. The core integrates an ARM 9 processor, a camera interface and two specific hardware blocks for image processing: a smart imaging coprocessor and an enhanced motion estimator. Both coprocessors have been designed using high-level synthesis tools taking the C programming language as a starting point. The resulting RTL code of each coprocessor has been synthesized and verified on an FPGA board. Two automotive and two mobile smart imaging applications are mapped onto the resulting smart imaging core. This mapping process of the original C++ applications onto the smart imaging core is also presented in this paper.

关键词： Automotive engineering Coprocessors Radar detection Vehicle detection Smart cameras Image processing High level synthesis Signal processing algorithms Face detection Telephony

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An architectural level design methodology for embedded face detection

An architectural level design methodology for embedded face ...

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international conference on hardware/software codesign and system synthesis (codes)

作者： R. Chellappa S. S. Bhattacharyya S. Saha W. Wolf G. Aggarwal J. Schlessman V. Kianzad ECE Department and Institute for Advanced Computer Studies University of Maryland College Park MD USA Department of Electrical Engineering Princeton University Princeton NJ USA

Face detection and recognition research has attracted great attention in recent years. Automatic face detection has great potential in a large array of application areas, including banking and security system access control, video surveillance, and multimedia information retrieval. In this paper, we discuss an architectural level design methodology for implementation of an embedded face detection system on a reconfigurable system on chip. We present models for performance estimation and validate these models with experimental values obtained from implementing our system on an FPGA platform. This modeling approach is shown to be efficient, accurate, and intuitive for designers to work with. Using this approach, we present several design options that trade-off various architectural features.

关键词： Design methodology Face detection Face recognition Banking Information security Access control Video surveillance Multimedia systems Information retrieval system-on-a-chip

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