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Using minimal minterms to represent programmability

Using minimal minterms to represent programmability

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international conference on hardware/software codesign and system synthesis (codes)

作者： Kurt Keutzer Scott J. Weber Electronics Research Laboratory University of California Berkeley USA

We address the problem of formally representing the programmability of a system. We define the programmability of a system as the set of valid execution paths that can be configured statically by software. We formally represent this programmability as a Boolean function. From this representation, we extract a subset of on-set minterms that we call minimal minterms. We prove that these minimal minterms represent the set of smallest schedulable atomic actions of the system, and that we can use a special generator relation to determine if subsets of these actions can be executed in parallel. We also prove that given an arbitrary Boolean function we can extract the minimal minterms and recreate the entire on-set by applying the generator relation to every element of the power set of the set of minimal minterms. Thus, the minimal minterms represent the complete instruction set supported by the system, and the generator relation represents the inherent parallelism among the instructions. Furthermore, we automatically generate the required software development tools and hardware implementation from this representation of programmability. Finally, we show that we can efficiently compute the minimal minterms and apply the generator relation to verify parallel executions on interesting data path systems.

关键词： Boolean functions Instruction sets Scheduling Computer aided instruction Power generation Parallel processing Programming hardware Data mining Algorithm design and analysis

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Retargetable generation of TLM bus interfaces for MP-SoC platforms

Retargetable generation of TLM bus interfaces for MP-SoC pla...

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international conference on hardware/software codesign and system synthesis (codes)

作者： Heinrich Meyr Rainer Leupers Achim Nohl Gerd Ascheid Tim Kogel Tom Michiels Andreas Wieferink Integrated Signal Processing Systems RWTH Aachen University Germany Coware Inc. CA USA

In order to meet flexibility, performance and energy efficiency constraints, future SoC (system-on-Chip) designs will contain an increasing number of heterogeneous processor cores combined with a complex communication architecture. Optimal platforms are obtained by customizing both computation and communication modules to the application's needs. In our design flow both kinds of SoC modules are automatically derived from abstract specifications. This work focuses on generating the communication adaptors, which are tailored to the processor as well as to the bus side. For early system simulation, the adaptors are capable of bridging an abstraction gap by implementing a bus interface state machine. The generated processor cores, adaptors and bus nodes are applied in the exemplary design of a JPEG decoding platform.

关键词： Energy efficiency Analytical models Computational modeling Interface states Network-on-a-chip Permission Signal generators Signal processing system-on-a-chip Computer architecture

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Novel architecture for loop acceleration: a case study

Novel architecture for loop acceleration: a case study

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international conference on hardware/software codesign and system synthesis (codes)

作者： Sri Parameswaran Newton Cheung Seng Lin Shee School of Computer Science and Engineering University of New South Wales Sydney Australia National Information and Communications Technology Australia NICTA Sydney Australia VaST Systems Technology Corporation Sydney Australia

In this paper, we show a novel approach to accelerate loops by tightly coupling a coprocessor to an ASIP. Latency hiding is used to exploit the parallelism available in this architecture. To illustrate the advantages of this approach, we investigate a JPEG encoding algorithm and accelerate one of its loop by implementing it in a coprocessor. We contrast the acceleration by implementing the critical segment as two different coprocessors and a set of customized instructions. The two different coprocessor approaches are: a high-level synthesis (HLS) approach; and a custom coprocessor approach. The HLS approach provides a faster method of generating coprocessors. We show that a loop performance improvement of 2.57x is achieved using the custom coprocessor approach, compared to 1.58x for the HLS approach and 1.33x for the customized instruction approach compared with just the main processor. Respective energy savings within the loop are 57%, 28% and 19%.

关键词： Acceleration Coprocessors Application specific processors Australia High level synthesis Delay Parallel processing Pipeline processing Computer architecture Energy consumption

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What will system level design be when it grows up?

What will system level design be when it grows up?

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international conference on hardware/software codesign and system synthesis (codes)

作者： Patrick Lysaght Peter Marwedel Mike Muller Daniel Gajski David Goodwin Jeff Welser Grant Martin Xilinx Research University of Dortmund Germany ARM UK UC Irvine Tensilica IBM

We have seen a growing new interest in Electronic system Level (ESL) architectures, design methods, tools and implementation fabrics in the last few years. But the picture of what types and approaches to building embedded systems will become the most widely-accepted norms in the future remains fuzzy at best. Everyone want to know where systems and system design is going "when it grows up", if it ever "grows up". Some of the key questions that need to be answered include which applications will be key system drivers, what SW&HW architectures will suit best, how programmable and configurable will they be, will systems designers need to deal with physical implementation issues or will that be hidden behind fabric abstractions and programming models, and what will those abstractions and models be? Moreover, will these abstractions stabilize and be still useful as the underlying technology keeps developing at high *** panel consists of proponents of a number of alternative visions for where we will end up, and how we will get there.

关键词： system-level design Fabrics Design methodology Buildings Embedded system Fuzzy systems Cities and towns

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Performance and power analysis of computer systems

Performance and power analysis of computer systems

引用

international conference on hardware/software codesign and system synthesis (codes)

作者： Trevor Mudge Bredt Family Professor of Engineering University of Michigan Ann Arbor USA

This tutorial will present an overview of techniques for architectural-level performance and power analysis of computer systems. It starts with a discussion of metrics for both performance and power, followed by an overview of some widely used benchmarks including SPEC, Mediabench, and MiBench. It then illustrates the use of these benchmarks with some published performance results. After this initial overview, the tutorial will focus on a discussion of architectural simulators to measure performance and *** simulators model systems on a (clock) cycle-by-cycle basis. Their operation will be illustrated with two popular examples: SimpleScalar and M5. Besides performance analysis, these simulators can be extended to include power estimation. Full simulations of complete applications can be extremely time consuming. The tutorial will explain how sampling techniques can be used to reduce simulation time. Finally, it will conclude with a discussion on the accuracy that can be expected from architectural simulators.

关键词： Performance analysis Power engineering computing Power engineering and energy Power measurement Power system modeling Clocks Analytical models Sampling methods Cities and towns

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An automated exploration framework for FPGA-based soft multiprocessor systems

An automated exploration framework for FPGA-based soft multi...

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international conference on hardware/software codesign and system synthesis (codes)

作者： Kurt Keutzer Kaushik Ravindran Nadathur Satish Yujia Jin University of California Berkeley CA USA

FPGA-based soft multiprocessors are viable system solutions for high performance applications. They provide a software abstraction to enable quick implementations on the FPGA. The multiprocessor can be customized for a target application to achieve high performance. Modern FPGAs provide the capacity to build a variety of micro-architectures composed of 20-50 processors, complex memory hierarchies, heterogeneous interconnection schemes and custom co-processors for performance critical operations. However, the diversity in the architectural design space makes it difficult to realize the performance potential of these systems. In this paper we develop an exploration framework to build efficient FPGA multiprocessors for a target application. Our main contribution is a tool based on Integer Linear Programming to explore micro-architectures and allocate application tasks to maximize throughput. Using this tool, we implement a soft multiprocessor for IPv4 packet forwarding that achieves a throughput of 2 Gbps, surpassing the performance of a carefully tuned hand design.

关键词： Multiprocessing systems Field programmable gate arrays Space exploration Application software Throughput Integer linear programming Coprocessors Algorithm design and analysis Permission Logic programming

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Satisfying real-time constraints with custom instructions

Satisfying real-time constraints with custom instructions

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international conference on hardware/software codesign and system synthesis (codes)

作者： Tulika Mitra Pan Yu School of Computing National University of Singapore Singapore

Instruction-set extensible processors allow an existing processor core to be extended with application-specific custom instructions. In this paper, we explore a novel application of instruction-set extensions to meet timing constraints in real-time embedded systems. In order to satisfy real-time constraints, the worst-case execution time (WCET) of a task should be reduced as opposed to its average-case execution time. Unfortunately, existing custom instruction selection techniques based on average-case profile information may not reduce a task's WCET. We first develop an Integer Linear Programming (ILP) formulation to choose optimal instruction-set extensions for reducing the WCET. However, ILP solutions for this problem are often too expensive to compute. Therefore, we also propose an efficient and scalable heuristic that obtains quite close to the optimal results. Experiment results indicate that suitable choice of custom instructions can reduce the WCET of our benchmark programs by as much as 42% (23.5% on an average).

关键词： Real time systems Embedded system Frequency Computer aided instruction Permission Processor scheduling Clocks Timing Integer linear programming Algorithm design and analysis

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SOMA: a tool for synthesizing and optimizing memory accesses in ASICs

SOMA: a tool for synthesizing and optimizing memory accesses...

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international conference on hardware/software codesign and system synthesis (codes)

作者： Seth Copen Goldstein Tiberiu Chelcea Tobias Bjerregaard Girish Venkataramani Carnegie Mellon University Pittsburgh USA TU Denmark Lyngby Denmark

Arbitrary memory dependencies and variable latency memory systems are major obstacles to the synthesis of large-scale ASIC systems in high-level synthesis. This paper presents SOMA, a synthesis framework for constructing Memory Access Network (MAN) architectures that inherently enforce memory consistency in the presence of dynamic memory access dependencies. A fundamental bottleneck in any such network is arbitrating between concurrent accesses to a shared memory resource. To alleviate this bottleneck, SOMA uses an application-specific concurrency analysis technique to predict the dynamic memory parallelism profile of the application. This is then used to customize the MAN architecture. Depending on the parallelism profile, the MAN may be optimized for latency, throughput or both. The optimized MAN is automatically synthesized into gate-level structural Verilog using a flexible library of network building blocks. SOMA has been successfully integrated into an automated C-to-hardware synthesis flow, which generates standard cell circuits from unrestricted ANSI-C programs. Post-layout experiments demonstrate that application specific MAN construction significantly improves power and performance.

关键词： Network synthesis Delay Integrated circuit synthesis Large-scale systems Application specific integrated circuits High level synthesis Concurrent computing Throughput hardware design languages Libraries

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Energy-efficient address translation for virtual memory support in low-power and real-time embedded processors

Energy-efficient address translation for virtual memory supp...

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international conference on hardware/software codesign and system synthesis (codes)

作者： Peter Petrov Xiangrong Zhou University of Maryland College Park USA

In this paper we present an application-driven address translation scheme for low-power and real-time embedded processors with virtual memory support. The power inefficiency and nondeterministic execution times of address-translation mechanisms have been major barriers in adopting and utilizing the benefits of virtual memory in embedded processors with low-power and real-time constraints. To address this problem, we propose a novel, Customizable Translation Table (CTT) organization, where application knowledge regarding the virtual memory footprint is used in order to eliminate conflicts in the hardware translation buffer and, thus, achieve tag-free address translation lookups. The set of virtual pages is partitioned into groups, such that for each group only a few of the least significant bits are used as an index to obtain the physical page number. We outline an efficient compile-time algorithm for identifying these groups and allocate their translation entries optimally into the CTT. The proposed methodology relies on the combined efforts of compiler, operating system, and hardware architecture to achieve a significant power reduction. The experiments that we have performed on a set of embedded applications show power reductions in the range of 55% to 80% compared to a general- purpose Translation Lookaside Buffer (TLB).

关键词： Energy efficiency hardware Virtual private networks Educational institutions Energy consumption Partitioning algorithms Operating systems Embedded system Memory management Kernel

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Power optimization for universal hash function data path using divide-and-concatenate technique

Power optimization for universal hash function data path usi...

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international conference on hardware/software codesign and system synthesis (codes)

作者： Ramesh Karri Bo Yang Department of Electrical and Computer Engineering Polytechnic University Brooklyn NY USA

We present an architecture level low power design technique called divide-and-concatenate for universal hash functions based on the following observations: (i) the power consumption of a w-bit array multiplier and associated universal hash data path decreases as O(w4) if its clock rate remains constant. (ii) two universal hash functions are equivalent if they have the same collision probability property. In the proposed approach we divide a w-bit data path (with collision probability 2-w) into two/four w/2-bit data paths (each with collision probability 2-w/2) and concatenate their results to construct an equivalent w-bit data path (with a collision probability 2-w). A popular low power technique that uses parallel data paths saves 62.10% dynamic power consumption incurring 102% area overhead. In contrast, the divide-and-concatenate technique saves 55.44% dynamic power consumption with only 16% area overhead.

关键词： hardware Energy consumption Clocks Design optimization Computer architecture Authentication Iterative algorithms Power system reliability Arithmetic Logic design

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