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Shift buffering technique for automatic code synthesis from synchronous dataflow graphs

Shift buffering technique for automatic code synthesis from ...

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international conference on hardware/software codesign and system synthesis (codes)

作者： Nikil Dutt Soonhoi Ha Hyunok Oh CECS University of California Irvine CA USA School of EECS Seoul National University Seoul South Korea

This paper proposes a new efficient buffer management technique called shift buffering for automatic code synthesis from synchronous dataflow graphs (SDF). Two previous buffer management methods, linear buffering and modulo (or circular) buffering, assume that samples are queued in the arc buffers in the arrival order and are accessed by moving the buffer indices. But both methods have significant overhead for general multi-rate systems: the linear buffering method requires large size buffers and the modulo buffering method needs run-time overhead of buffer index computation. The proposed shift buffering method shifts samples rather than moving buffer indices. We develop optimal shift buffering algorithms to minimize the number of shifted samples. Our experimental results show that the proposed algorithm saves up to 90% of performance overhead while requiring the same amount of buffer memory as modulo buffering. Considering the sample copy overhead, shift buffering is applicable when memory size is more crucial than performance overhead, and the shifting overhead is less than the modulo addressing overhead. Another advantage of the shift buffering technique is that it supports the library code written with the linear buffering assumption, which is practically more important.

关键词： Signal processing algorithms Runtime Application software Embedded system software libraries software design Pipelines Signal design Digital signal processing Signal synthesis

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Highly flexible multi-mode system synthesis

Highly flexible multi-mode system synthesis

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international conference on hardware/software codesign and system synthesis (codes)

作者： John Lach Vinu Vijay Kumar Texas Instruments Inc. Stafford TX USA Department of Electrical & Computer Engineering University of Virginia Charlottesville VA USA

Multi-mode systems have emerged as an area- and power-efficient approach to implementing multiple time-wise mutually exclusive algorithms and applications in a single hardware space. These systems have limited flexibility and temporal separation between modes is achieved by changing only the dataflow between components. This paper presents a synthesis methodology for integrating flexible components and controllers into primarily fixed logic multi-mode systems thereby increasing their overall flexibility and efficiency. The components are built using a technique called small-scale reconfigurability that provides the necessary flexibility without the penalties associated with general-purpose reconfigurable logic. The reconfiguration latency is small enabling both inter-mode and intra-mode reconfiguration of components. Datapath and controller area and power consumption are reduced beyond what is provided in current multi-mode systems using this methodology, without sacrificing performance. The results show an average 7% reduction in datapath component area, 26% reduction in register area, 36% reduction in interconnect MUX cost, and a 68% reduction in the number of controller signals for a set of benchmark 32-bit signal processing applications. There is also an average 38% increase in component utilization.

关键词： Reconfigurable logic Signal processing Signal processing algorithms hardware Control system synthesis Delay Control systems Energy consumption Power system interconnection Costs

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CRAMES: compressed RAM for embedded systems

CRAMES: compressed RAM for embedded systems

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international conference on hardware/software codesign and system synthesis (codes)

作者： Haris Lekatsas Robert P. Dick Srimat Chakradhar Lei Yang Northwestern University Evanston IL USA NEC Laboratories of America Inc. Princeton NJ USA

Memory is a scarce resource in many embedded systems. Increasing memory often increases packaging and cooling costs, size, and energy consumption. This paper presents CRAMES, an efficient software-based RAM compression technique for embedded systems. The goal of CRAMES is to dramatically increase effective memory capacity without hardware design changes, while maintaining high performance and low energy consumption. To achieve this goal, CRAMES takes advantage of an operating system's virtual memory infrastructure by storing swapped-out pages in compressed format. It dynamically adjusts the size of the compressed RAM area, protecting applications capable of running without it from performance or energy consumption penalties. In addition to compressing working data sets, CRAMES also enables efficient in-RAM filesystem compression, thereby further increasing RAM capacity. CRAMES was implemented as a loadable module for the Linux kernel and evaluated on a battery-powered embedded system. Experimental results indicate that CRAMES is capable of doubling the amount of RAM available to applications. Execution time and energy consumption for a broad range of examples increase only slightly, by averages of 0.35% and 4.79%. In addition, this work identifies the software-based compression algorithms that are most appropriate for low-power embedded systems.

关键词： Embedded system Read-write memory Random access memory Energy consumption Packaging Cooling Costs hardware Protection Linux

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A cycle-accurate compilation algorithm for custom pipelined datapaths

A cycle-accurate compilation algorithm for custom pipelined ...

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international conference on hardware/software codesign and system synthesis (codes)

作者： Daniel Gajski Mehrdad Reshadi Center for Embedded Computer Systems CECS University of California Irvine CA USA

Traditional high level synthesis (HLS) techniques generate a datapath and controller for a given behavioral description. The growing wiring cost and delay of today technologies require aggressive optimizations, such as interconnect pipelining, that cannot be done after generating the datapath and without invalidating the schedule. On the other hand, the increasing manufacturing complexities demand approaches that favor design for manufacturability (DFM).To address these problems we propose an approach in which the datapath of the architecture is fully allocated before scheduling and binding. We compile a C program directly to the datapath and generate the controller. We can support the entire ANSI C syntax because the datapath can be as complex as the datapath of a processor. Since there is no instruction abstraction in this architecture we call it No-Instruction-Set-Computer (NISC). As the first step towards realization of a NISC-based design flow, we present an algorithm that maps an application on a given datapath by performing scheduling and binding simultaneously. With this algorithm, we achieved up to 70% speedup on a NISC with a datapath similar to that of MIPS, compared to a MIPS gcc compiler. It also efficiently handles different datapath features such as pipelining, forwarding and multi-cycle units.

关键词： Job shop scheduling High level synthesis Pipeline processing Manufacturing Processor scheduling Wiring Cost function Delay Algorithm design and analysis Scheduling algorithm

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Memory access optimizations in instruction-set simulators

Memory access optimizations in instruction-set simulators

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international conference on hardware/software codesign and system synthesis (codes)

作者： Prabhat Mishra Mehrdad Reshadi Center for Embedded Computer Systems (CECS) University of California Irvine Irvine CA USA Computer and Information Science and Engineering University of Florida Gainesville FL USA

Design of programmable processors and embedded applications requires instruction-set simulators for early exploration and validation of candidate architectures. Interpretive simulators are widely used in embedded systems design. One of the key performance bottlenecks in interpretive simulation is the instruction and data memory access translation between host and target machines. The simulators must maintain and update the status of the simulated processor including memory and register values. A major challenge in the simulation is to efficiently map the target address space to the host address space. This paper presents two optimization techniques that aggressively utilize the spatial locality of the instruction and data accesses in interpretive simulation: signature based address mapping for optimizing general memory accesses; and incremental instruction fetch for optimizing instruction accesses. To demonstrate the utility of this approach we applied these techniques on SimpleScalar simulator, and obtained up to 30% performance improvement. Our techniques complement the recently proposed optimizations (JIT-CCS [1] and IS-CS [2]) and further improve the performance (up to 89%) on ARM7 and Sparc processors.

关键词： Decoding Computational modeling Runtime Computer aided instruction Embedded computing Embedded system Permission Computer simulation Information science Process design

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Future wireless convergence platforms 05

Future wireless convergence platforms

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international conference on hardware/software codesign and system synthesis (codes)

作者： Mayan Moudgill Michael Schulte Stamatis Vassiliadis Daniel Iancu Gary Nacer Michael Samori Sanjay Jintukar Stuart Stanley Tanuj Raja John Glossner Sandbridge Technologies Inc. White Plains NY USA Sandbridge Technologies Inc. White Plains NY

ISBN: (纸本)9781595931610

As wireless platforms converge to multimedia systems, architectures must converge to support voice, data, and video applications. From a processor architecture perspective, support for signal processing (both audio and video), control code, and Java execution will be required in a convergent device. Traditionally, wireless communications systems have been implemented in hardware. Convergent devices must be able to roam seamlessly across multiple communications systems. To avoid excessive hardware costs, a software Defined Radio (SDR) approach offers a programmable and dynamically reconfigurable method of reusing hardware to implement physical layer processing. In this paper, we discuss trends in wireless platforms which are inherently convergence platforms. We also present the Sandbridge state-of-the-art example platform that supports both communications and multimedia applications processing. The architecture efficiently executes Java, Digital Signal Processing (DSP), and control code. Architectural features that reduce power dissipation and enable real-time processing are described. All of the communications and multimedia processing is executed completely in software without specialized hardware support. The processor is programmed in C with supercomputer-class compiler support for automatic vectorization, multithreading, and DSP semantic analysis.

关键词： Convergence hardware Digital signal processing Computer architecture Communication system control Java Multimedia communication Multimedia systems Video signal processing Wireless communication

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An efficient direct mapped instruction cache for application-specific embedded systems

An efficient direct mapped instruction cache for application...

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international conference on hardware/software codesign and system synthesis (codes)

作者： Chuanjun Zhang Computer Science and Electrical Engineering Department University of Missouri Kansas City Kansas City MO USA

Caches may consume half of a microprocessor's total power and cache misses incur accessing off-chip memory, which is both time consuming and energy costly. Therefore, minimizing cache power consumption and reducing cache misses are important to reduce total energy consumption of embedded systems. Direct mapped caches consume much less power than that of same sized set associative caches but with a poor hit rate on average. Through experiments, we observe that memory space of direct mapped instruction caches is not used efficiently in most embedded applications. We design an efficient cache - a configurable instruction cache that can be tuned to utilize the cache sets efficiently for a particular application such that cache memory is exploited more efficiently by index remapping. Experiments on 11 benchmarks drawn from Mediabench show that the efficient cache achieves almost the same miss rate as a conventional two-way set associative cache on average and with total memory-access energy savings of 30% compared with a conventional two-way set associative cache.

关键词： Embedded system Energy consumption Delta modulation Cache memory Algorithm design and analysis Cities and towns Computer science Clocks Frequency Application specific processors

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High-level synthesis for large bit-width multipliers on FPGAs: a case study

High-level synthesis for large bit-width multipliers on FPGA...

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international conference on hardware/software codesign and system synthesis (codes)

作者： James P. Davis Duncan A. Buell Siddhaveerasharan Devarkal Gang Quan Department of Computer Science and Engineering University of South Carolina Columbia SC USA

In this paper, we present the analysis, design and implementation of an estimator to realize large bit width unsigned integer multiplier units. Larger multiplier units are required for cryptography and error correction circuits for more secure and reliable transmissions over highly insecure and/or noisy channels in networking and multimedia applications. The design space for these circuits is very large when integer multiplication on large operands is carried out hierarchically. In this paper, we explore automated synthesis of high bit-width unsigned integer multiplier circuits by defining and validating an estimator function used in search and analysis of the design space of such circuits. We focus on analysis of a hybrid hierarchical multiplier scheme that combines the throughput advantages of parallel multipliers and the resource cost-effectiveness of serial ones. We present an analytical model that rapidly predicts timing and resource usage for selected model candidates. We evaluate the estimator model in the design of a practical application, a 256-bit elliptic curve adder implemented on a Xilinx FPGA fabric. We show that our estimator allows implementation of fast, efficient circuits, where resultant designs provide order-of-magnitude performance improvements when compared with that of software implementations on a high performance computing platform.

关键词： High level synthesis Field programmable gate arrays Elliptic curve cryptography Error correction Circuit noise Circuit synthesis Network synthesis Throughput Analytical models Timing

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Designing real-time H.264 decoders with dataflow architectures

Designing real-time H.264 decoders with dataflow architectur...

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international conference on hardware/software codesign and system synthesis (codes)

作者： Suleyman Sair Youngsoo Kim Department of Electrical and Computer Engineering NC State University USA

High performance microprocessors are designed with general-purpose applications in mind. When it comes to embedded applications, these architectures typically perform control-intensive tasks in a system-on-Chip (SoC) design. But they are significantly inefficient for data-intensive tasks such as video encoding/decoding. Although configurable processors fill this gap by complementing the existing functional units with instruction extensions, their performance lags behind the needs of real-time embedded tasks. In this paper, we evaluate the performance potential of a dataflow processor for H.264 video decoding. We first profile the H.264 application to capture the amount of data traffic among modules. We use this information to guide the placement of H.264 modules in the WaveScalar dataflow architecture. A simulated annealing based placement algorithm produces the final placement aiming to optimize the communication costs between the modules in the dataflow architecture. In addition to outperforming contemporary embedded and customized processors, our simulated annealing guided design shows a speedup of 13% in execution time over the original WaveScalar architecture. With our dataflow design methodology, emerging embedded applications requiring several GOPS to meet real-time constraints can be drafted within a reasonable amount of design time.

关键词： Decoding Computer architecture Design methodology Application software Acceleration Encoding Simulated annealing Permission Microprocessors Control systems

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Aggregating processor free time for energy reduction

Aggregating processor free time for energy reduction

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international conference on hardware/software codesign and system synthesis (codes)

作者： Alex Nicolau Nikil Dutt Eugene Earlie Aviral Shrivastava Center for Embedded Computer Systems School of Information and Computer Science University of California Irvine CA USA Strategic CAD Laboratories Intel Corporation Hudson MA USA

Even after carefully tuning the memory characteristics to the application properties and the processor speed, during the execution of real applications there are times when the processor stalls, waiting for data from the memory. Processor stall can be used to increase the throughput by temporarily switching to a different thread of execution, or reduce the power and energy consumption by temporarily switching the processor to low-power mode. However, any such technique has a performance overhead in terms of switching time. Even though over the execution of an application the processor is stalled for a considerable amount of time, each stall duration is too small to profitably perform any state switch. In this paper, we present code transformations to aggregate processor free time. Our experiments on the Intel XScale and Stream kernels show that up to 50,000 processor cycles can be aggregated, and used to profitably switch the processor to low-power mode. We further show that our code transformations can switch the processor to low-power mode for up to 75% of kernel runtime, achieving up to 18% of processor energy savings on multimedia applications. Our technique requires minimal architectural modifications and incurs negligible ( < 1%) performance loss.

关键词： Switches Embedded computing Application software Embedded system Algorithm design and analysis Energy consumption Kernel Delay Permission Computer science

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