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Design and programming of embedded multiprocessors: an interface-centric approach 04

Design and programming of embedded multiprocessors: an inter...

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international conference on hardware/software codesign and system synthesis (codes)

作者： P. van der Wolf E. de Kock T. Henriksson W. Kruijtzer G. Essink Philips Research Laboratories Eindhoven Netherlands

ISBN: (纸本)9781581139372

We present design technology for the structured design and programming of embedded multi-processor systems. It comprises a task-level interface that can be used both for developing parallel application models and as a platform interface for implementing applications on multi-processor architectures. Associated mapping technology supports refinement of application models towards implementation. By linking application development and implementation aspects, the technology integrates the specification and design phases in the MPSoC design process. Two design cases demonstrate the efficient implementation of the platform interface on different architectures. Industry-wide standardization of a task-level interface can facilitate reuse of function-specific hardware/software modules across companies.

关键词： hardware Application software Computer architecture Refining Process design Standardization Permission Joining processes Computer industry Parallel architectures

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Organic computing - on the feasibility of controlled emergence 04

Organic computing - on the feasibility of controlled emergen...

引用

international conference on hardware/software codesign and system synthesis (codes)

作者： C. Muller-Schloer Institute of Systems Engineering-System and Computer Architecture (SRA) Universität Hannover Hanover Germany

ISBN: (纸本)9781581139372

This work gives an introduction to the research area of organic computing and shows chances, opportunities and problems currently tackled by researchers. First the visions that lead to this research area are discussed briefly. It is shown that the notion of emergence, a central phenomenon in organic computing, is a typical bottom-up effect with the interesting property of generating order from randomness. The classical design, however, is a top-down process. This apparent contradiction can be overcome by introducing so-called observer/controller architectures leading to the possibility to controlled emergence. The paper concludes with a description of current research problems in organic computing.

关键词： Telecommunication computing Computer architecture Artificial intelligence Application software Permission Web and internet services systems engineering and theory Mobile computing Intelligent agent Multiagent systems

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Automatic synthesis of system on chip multiprocessor architectures for process networks 04

Automatic synthesis of system on chip multiprocessor archite...

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international conference on hardware/software codesign and system synthesis (codes)

作者： B.K. Dwivedi A. Kumar M. Balakrishnan Dept. of Computer Science and Engineering Indian Institute of Technology Delhi New Delhi India

ISBN: (纸本)9781581139372

We present an approach for automatic synthesis of system on chip (SoC) multiprocessor architectures for applications expressed as process networks. Our approach is targeted towards design space exploration (DSE) and thus the speed of synthesis is of critical interest. The focus here is on the problem of resource allocation and binding with a view to optimize cost under performance constraints. Our approach exploits adjacency relation of processes and uses a dynamic programming based algorithm to synthesize the architecture including interconnection network. We have done a number of experiments on real as well as randomly generated process networks. The results have been compared with an optimal MILP formulation. They conclusively show that this approach is fast as well as effective and can be employed for DSE.

关键词： Network synthesis system-on-a-chip Space exploration Resource management Constraint optimization Cost function Dynamic programming Heuristic algorithms Multiprocessor interconnection networks Random number generation

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Secure and safety-critical vs. insecure, non safety-critical embedded systems: do they require completely different design approaches? 04

Secure and safety-critical vs. insecure, non safety-critical...

引用

international conference on hardware/software codesign and system synthesis (codes)

作者： P. Marwedel C. Gebotys University of Dortmund and ICD University of Waterloo

ISBN: (纸本)9781581139372

As we move forward into the era of ubiquitous pervasive computing, the design of secure safety-critical systems will become increasingly complex. For example, future automobiles will become the ultimate mobile wireless device containing a distributed network with multiple vendor software and hardware. However the carýs embedded software which is expected to increase in size by 100 fold, will create a significant impact on the overall system safety. Furthermore wireless communications may create the possibility of terrorists or attackers gaining control of the automobile, hence security is also an important issue. How will designers cope with this complexity while at the same time ensure safety and security? Will new design approaches be required? Or can current design methodologies be used with new metrics, safety and security? This panel will bring together experts from the safety-critical industry, security industry, and experts from the insecure non-safety critical industry.

关键词： Embedded system Automobiles software safety Communication system security hardware Embedded software Hazards Smart cards Immune system software systems

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Optimizing the memory bandwidth with loop fusion

Optimizing the memory bandwidth with loop fusion

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international conference on hardware/software codesign and system synthesis (codes)

作者： P. Marchal F. Catthoor J.I. Gomez KU Leuven Heverlee Belgium DACYA/UCM Madrid Spain

The memory bandwidth largely determines the performance and energy cost of embedded systems. At the compiler level, several techniques improve the memory bandwidth at the scope of a basic block, but often fail to exploit all. We propose a technique to optimize the memory bandwidth across the boundaries of a basic block. Our technique incrementally fuses loops to better use the available bandwidth. The resulting performance depends on how the data is assigned to the memories of the memory layer. At the same time, the assignment also strongly influences the energy cost. Therefore, we combine in our approach the fusion and assignment decisions. Designers can use our output to trade-off the energy cost with the system's performance.

关键词： Bandwidth Costs Fuses Processor scheduling Permission Embedded system Algorithm design and analysis Delay Optimizing compilers Data structures

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system-on-chip validation using UML and CWL 04

System-on-chip validation using UML and CWL

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international conference on hardware/software codesign and system synthesis (codes)

作者： Q. Zhu R. Oishi T. Hasenawa T. Nakata Fujitsu Laboratories LTD Nakahara-ku Kawasaki Japan

ISBN: (纸本)9781581139372

A novel method for high-level specification and validation of SoC designs using UML is proposed. UML is introduced as a formal model of specification for SoC design. The consistency and completeness of the specification is validated based on the formal UML model. The implementation is validated by a systematic derivation of test scenarios and specification based coverage metrics from the UML model. The method has been applied to the design of a new media-processing chip for mobile devices. The application of the method shows that it is not only effective for finding logical errors in the implementation, but also eliminates errors due to inconsistency and incompleteness of the specification.

关键词： Unified modeling language Object oriented modeling Protocols Process design Computer architecture Timing Programming Specification languages Intellectual property Testing

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Memory accesses management during high level synthesis 04

Memory accesses management during high level synthesis

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international conference on hardware/software codesign and system synthesis (codes)

作者： G. Corre E. Senn P. Bornel N. Julien E. Martin LESTER University of South Brittany LORIENT cedex France LESTER South Brittany Univ. Lorient France

ISBN: (纸本)9781581139372

We introduce an approach to take into account the memory architecture and the memory mapping in behavioral synthesis. We formalize the memory mapping as a set of constraints for the synthesis, and defined a memory constraint graph and an accessibility criterion to be used in the scheduling step. We present a strategy for implementing signals (ageing vectors). We formalize the maturing process and explain how it may generate memory conflicts over several iterations of the algorithm. The final compatibility graph indicates the set of valid mappings for every signal. Several experiments are performed with our HLS tool GAUT. Our scheduling algorithm exhibits a relatively low complexity that permits to tackle complex designs in a reasonable time.

关键词： Memory management High level synthesis Signal synthesis Algorithm design and analysis Scheduling algorithm Flow graphs Costs Registers Memory architecture Aging

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A novel deadlock avoidance algorithm and its hardware implementation

A novel deadlock avoidance algorithm and its hardware implem...

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international conference on hardware/software codesign and system synthesis (codes)

作者： Jaehwan Lee V.J. Mooney Georgia Institute of Technology Atlanta GA USA

This work proposes a deadlock avoidance algorithm (DAA) and its hardware implementation, the deadlock avoidance unit (DAU), as an intellectual property (IP) core that provides a mechanism for very fast and automatic deadlock avoidance in multiprocessor system-on-a-chip (MP-SoC) with multiple (e.g., 10) processing elements and multiple (e.g., 40) resources. The DAU avoids deadlock by not allowing any grant or request that leads to a deadlock. In case of livelock, the DAU asks one of the processes involved in the livelock to release resource(s) so that the livelock can also be resolved. We simulated two realistic examples that can benefit from the DAU, and demonstrated that the DAU not only avoids deadlock in a few clock cycles but also achieves a 37% speed-up of application execution time over avoiding deadlock in software. Finally, the SoC area overhead due to the DAU is small, under 0.01% in our example.

关键词： system recovery hardware system-on-a-chip Resource management Application software Algorithm design and analysis Permission Intellectual property Multiprocessing systems Clocks

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Facilitating reuse in hardware models with enhanced type inference 04

Facilitating reuse in hardware models with enhanced type inf...

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international conference on hardware/software codesign and system synthesis (codes)

作者： M. Vachharajani N. Vachharajani S. Malik D.I. August Departments of Computer Science and Electrical Engineering Princeton University Princeton NJ USA

ISBN: (纸本)9781581139372

High-level hardware modeling is an essential, yet time-consuming, part of system design. However, effective component-based reuse in hardware modeling languages can reduce model construction time and enable the exploration of more design alternatives, leading to better designs. While component overloading and parametric polymorphism are critical for effective component-base reuse, no existing modeling language supports both. The lack of these features creates overhead for designers that discourages reuse, negating any benefits of reuse. This work presents a type system which supports both component overloading and parametric polymorphism. It proves that performing type inference for any such system is NP-complete and presents a heuristic that works efficiently in practice. The result is a type system and type inference algorithm that can encourage reuse, reduce design specification time, and lead to better designs.

关键词： hardware Algorithm design and analysis Concrete Inference algorithms Computer languages Space exploration Computer science Lead time reduction Buildings Permission

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A timing-accurate HW/SW cosimulation of an ISS with systemC 04

A timing-accurate HW/SW cosimulation of an ISS with SystemC

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international conference on hardware/software codesign and system synthesis (codes)

作者： L. Formaggio F. Fummi G. Pravadelli Dipartirnento di lnformatica Università di Verona Verona Italy

ISBN: (纸本)9781581139372

The paper presents a system level co-simulation methodology for modeling, validating, and analyzing the performance of embedded systems. The proposed solution relies on the integration between an instruction set simulator (ISS) and the systemC simulation kernel. In this way, the ISS is used to abstract the model of the real programmable device where the SW should run, while systemC is used to model HW components that interact with the SW. A correct validation of such an architecture is infeasible without taking care of timing information. Thus, the paper proposes an effective timing synchronization mechanism, which uses timing information of an ISS (or a board) to synchronize the systemC simulation.

关键词： Timing Performance analysis Embedded system Engines hardware design languages Kernel system-level design Permission Discrete event simulation Computer languages

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