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检索条件"任意字段=2014 International Conference on Hardware/Software Codesign and System Synthesis, CODES ISSS 2014"

共 593 条记录，以下是51-60 订阅

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A New hardware Trojan Design: Distinguishing Between Trigger Inputs and Functional Inputs Is Difficult: Work-in-Progress

A New Hardware Trojan Design: Distinguishing Between Trigger...

引用

international conference on hardware/software codesign and system synthesis (codes+isss)

作者： Ge, Minghui Zhang, Ying Li, Sen Yao, Jiaqi Mao, Zhiming Chen, Xin Nanjing Univ Aeronaut & Astronaut NUAA Dept Elect & Informat Engn EIE Nanjing Peoples R China

ISBN: (纸本)9781728191980

In this paper, we propose a new hardware Trojan Design. This design makes all HT trigger inputs have the same impact as functional inputs on output signals. It is difficult to distinguish between trigger inputs and functional inputs. Simultaneously, trigger inputs will not be identified as redundant inputs. This approach can defeat the existing detection methods which identify weakly affecting and red Cant trigger inputs across multiple sequential levels. The proposed HT has stealthiness and general applicability.

关键词： hardware trojan trigger inputs functional inputs

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Work-in-Progress: Offloading Cache Configuration Prediction to an FPGA for hardware Speedup and Overhead Reduction

Work-in-Progress: Offloading Cache Configuration Prediction ...

引用

Embedded systems Week / Int Conf on Compilers, Architecture, and synthesis for Embedded systems (CASES) / international conference on hardware/software codesign and system synthesis (codes+isss) / Int Conf on Embedded software (EMSOFT)

作者： Vazquez, Ruben Gordon-Ross, Ann Stitt, Greg Univ Florida Dept Elect & Comp Engn Gainesville FL 32611 USA

In this paper, we present our cache configuration prediction methodology offloaded to an FPGA for improved performance and hardware overhead reduction, while maintaining cache configuration predictions within 5% of th... 详细信息

ISBN: (纸本)9781450369237

关键词： cache configurable artificial neural network mobile devices FPGA phases machine learning

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Attention-Based Secure Feature Extraction in Near Sensor Processing: Work-in-Progress

Attention-Based Secure Feature Extraction in Near Sensor Pro...

引用

international conference on hardware/software codesign and system synthesis (codes+isss)

作者： Bhowmik, Pankaj Pantho, Md Jubaer Hossain Saha, Sujan Kumar Bobda, Christophe Univ Florida Dept Elect & Comp Engn Gainesville FL 32611 USA

ISBN: (纸本)9781728191980

This paper presents a secure hardware architecture of an image sensor to accelerate feature extraction using region-level parallelism. For each logical region, the design includes a region processing unit (RPU) with an attention module (AM). The AM activates the processing in the RPU if there are no spatiotemporal redundancies. It reduces power consumption and data volume by utilizing the concepts of predictive coding. Also, every RPU has a crypto-core driven by the AM to withstand against adversaries. Simulation results show we can save 89.70% power with a significant speedup.

关键词： Pixel Level Processing SIFT Attention Module Image Sensor hardware security FPGA ASIC

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Heatmap-Aware Low-Cost Design to Resist Adversarial Attacks: Work-in-Progress

Heatmap-Aware Low-Cost Design to Resist Adversarial Attacks:...

引用

international conference on hardware/software codesign and system synthesis (codes+isss)

作者： He, Zhiyuan Jiang, Wei Zhan, Jinyu Wang, Xupeng We, Xiangyu Univ Elect Sci & Technol China Sch Informat & Software Engn Chengdu Peoples R China

ISBN: (纸本)9781728191980

It is a challenging task to resist adversarial attacks due to the imperceptibility of adversarial examples. The passive defense method is developed based on a series of input transformations and has achieved a promising result, which however suffers from a high computation cost. In this paper, we design a new heatmap-aware method to defend adversarial attacks, leading to a significant decrease in the time cost. To he specific, we compute the classification importance from each part of the input to obtain the heatmap of the data, and the key areas of classification are extracted according to the heatmap. A series of transformations are applied to the key areas of the classification, which reduces the amount of data to be processed and thus reduces the time cost. A set of preliminary experiments are conducted to testify the effectiveness of the proposed approach.

关键词： Costs

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Formal Verification of GCSE in the Scheduling of High-level synthesis: Work-in-Progress

Formal Verification of GCSE in the Scheduling of High-level ...

引用

international conference on hardware/software codesign and system synthesis (codes+isss)

作者： Hu, Jian Hu, Yongyang Yu, Long Wang, Wentao Yang, Haitao Kang, Yun Cheng, Jie Natl Univ Def Technol Res Inst 63 Nanjing Peoples R China Natl Univ Def Technol Coll Comp Sci & Technol Changsha Peoples R China

ISBN: (纸本)9781728191980

High-level synthesis entails application of a sequence of transformations to compile a high-level description of a hardware design (e.g., in C/C++/systemC) into a register-transfer level (RTL) implementation. However, an error may exist in the RTL implementation from the compiler in the high-level synthesis due to the complex and error prone compiling process. Global common subexpression elimination (GCSE) is a commonly used code motion technique in the scheduling of high-level synthesis. In this paper, we present an equivalence checking method to verify GCSE in the scheduling of high-level synthesis by enhancing the path equivalence criteria. The initial experimental results demonstrate our method can indeed verify the GCSE which has not been properly addressed in the past.

关键词： Equivalence Checking High-level synthesis FSMD Global Common Subexpression Elimination

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Work-in-Progress: A Simulation Framework for Domain-Specific system-on-Chips

Work-in-Progress: A Simulation Framework for Domain-Specific...

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作者： Arda, Samet E. Anish, N. K. Goksoy, A. Alper Mack, Joshua Kumbhare, Nirmal Sartor, Anderson L. Akoglu, Ali Marculescu, Radu Ogras, Umit Y. Arizona State Univ Sch Elect Comp & Energy Engn Tempe AZ 85287 USA Univ Arizona Elect & Comp Engn Tucson AZ USA Carnegie Mellon Univ Elect & Comp Engn Pittsburgh PA 15213 USA

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An Energy-aware Spiking Neural Network hardware Mapping based on Particle Swarm Optimization and Genetic Algorithm

An Energy-aware Spiking Neural Network Hardware Mapping base...

引用

international conference on hardware/software codesign and system synthesis (codes+isss)

作者： Liu, Junxiu Huang, Xingyue Jiang, Dong Luo, Yuling Guangxi Normal Univ Sch Elect Engn Guilin Peoples R China

ISBN: (纸本)9781728191980

Spiking Neuron Network (SNN) is a biological neural network model which shows great capability in the time series data processing and pattern recognition etc. according to the recent research. It has been implemented in hardware system with a good scalability, where the Networks-on-Chip (NoC) interconnection strategy is widely used for the data communications between the neurons. The mapping between a SNN and a NoC hardware system is one of the challenge for the development of the hardware SNNs. In this paper, a hybrid Particle Swarm Optimization (PSO) algorithm for hardware SNN mapping is proposed with the object of minimizing the energy consumption. Compared to the conventional PSO, it can search the mapping solutions through three directions which can speed up the finding. In the meantime, the Genetic Algorithm (GA) is combined to provide the mutation operation to avoid converging to the local optimum. A typical hardware SNN is used as the testbench and results show that an effective hardware SNN mapping is obtained with a low energy consumption, and local optimum is avoided compared to other approaches.

关键词： Spiking neural networks hardware implementation Networks-on-Chip Energy consumption

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Work-in-Progress: EAST-DNN: Expediting Architectural SimulaTions Using Deep Neural Networks

Work-in-Progress: EAST-DNN: Expediting Architectural SimulaT...

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作者： Dutt, Arko Narasimman, Govind Jie, Lin Chandrasekhar, Vijay Ramaseshan Sabry, Mohamed M. NTU Singapore Singapore Singapore A STAR I2R Singapore Singapore Singapore

ISBN: (纸本)9781450369237

A rapid and accurate architectural simulator is a cornerstone for an efficient design-space exploration of computing systems. In this paper, we introduce EAST-DNN, a feed-forward deep neural network, to accelerate architectural simulations. EAST-DNN achieves > 106 x speedup with an average prediction error of 4.3% over the baseline simulator. It also achieves an average of 2x better accuracy with at least 2.3x speedup compared to state-of-the-art.

关键词： Deep Neural Network hardware Accelerators

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Accelerating Queries of MongoDB by an FPGA-based Storage Engine: Work-in-Progress

Accelerating Queries of MongoDB by an FPGA-based Storage Eng...

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international conference on hardware/software codesign and system synthesis (codes+isss)

作者： Zhan, Jinyu Wu, Junting Jiang, Wei Li, Ying Zhu, Jianping Univ Elect Sci & Technol China Sch Informat & Software Engn Chengdu Peoples R China Tencent Technol Shenzhen Co Ltd Shenzhen Peoples R China

ISBN: (纸本)9781728191980

In this paper, we propose a storage engine for MongoDB to accelerate the queries and reduce the memory usage. An FPGA-based query accelerator is deployed to speed up the queries while hot data is migrated from memory to SSD to reduce memory occupancy by our storage engine. Moreover, multiple query tasks of MongoDB are performed in parallel and query conditions are parameterized to support diversified queries. Based on TPC-H benchmark and Tencent data set, experimental results demonstrate that our storage engine can achieve higher query efficiency (saving up to 63.5% time overhead) and lower memory occupancy (reducing up to 73.4% memory usage) compared with traditional MongoDB.

关键词： Field programmable gate arrays (FPGA)

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Work-in-Progress: Fine-Grained Acceleration using Runtime Integrated Custom Execution (RICE)

Work-in-Progress: Fine-Grained Acceleration using Runtime In...

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作者： Pakanati, Leela McMichen, John T. Estrada, Zachary Rose Hulman Inst Technol Terre Haute IN 47803 USA

ISBN: (纸本)9781450369251

Runtime Integrated Custom Execution (RICE) relocates traditional peripheral reconfigurable acceleration devices into the pipeline of the processor. This relocation unlocks fine-grained acceleration previously impeded by communication overhead to a peripheral accelerator. Preliminary simulation results on a subset of the PARSEC benchmark suite shows promise for RICE in HPC applications.

关键词： RISC-V hardware Acceleration FPGA hardware-software Co-Design Gem5 PARSEC

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