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检索条件"任意字段=2014 International Conference on Hardware/Software Codesign and System Synthesis, CODES ISSS 2014"

共 593 条记录，以下是61-70 订阅

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Meta-Chain: User-Aware Cross-Layer Space Allocation Strategy for Blockchain Storage systems: Work-in-Progress

Meta-Chain: User-Aware Cross-Layer Space Allocation Strategy...

引用

international conference on hardware/software codesign and system synthesis (codes+isss)

作者： Liao, Jing Li, Zhengda Wang, Yi Shenzhen Univ Coll Comp Sci & Software Engn Shenzhen Peoples R China Shenzhen Univ Natl Engn Lab Big Data Syst Comp Technol Shenzhen Peoples R China

ISBN: (纸本)9781728191980

Current LSM-Tree-based blockchain storage system will assign the data from multiple system users to the same disk drive. This will lead to the inefficient usage of physical spaces in disk and cause extra compaction operations for LSM-Tree. This paper presents Meta Chain, a user-aware cross-layer space allocation strategy for blockchain storage systems. As a cross-layer design, Meta-Chain redesigns the organization of LSM-Tree and utilizes the rich functionalities provided by open-channel SSD. Experimental results show that Meta-Chain can effectively reduce write amplification and extend the lifetime of SSD in comparison with representative schemes.

关键词： Blockchain Storage system LSM-Tree Flash Memory Space Allocation Address Translation

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A New hardware Trojan Design: Distinguishing Between Trigger Inputs and Functional Inputs Is Difficult: Work-in-Progress

A New Hardware Trojan Design: Distinguishing Between Trigger...

引用

international conference on hardware/software codesign and system synthesis (codes)

作者： Minghui Ge Ying Zhang Sen Li Jiaqi Yao Zhiming Mao Xin Chen Nanjing University of Aeronautics and Astronautics (NUAA) Nanjing China

ISBN: (数字)9781728191980

ISBN: (纸本)9781728191997

In this paper, we propose a new hardware Trojan Design. This design makes all HT trigger inputs have the same impact as functional inputs on output signals. It is difficult to distinguish between trigger inputs and functional inputs. Simultaneously, trigger inputs will not be identified as redundant inputs. This approach can defeat the existing detection methods which identify weakly-affecting and redundant trigger inputs across multiple sequential levels. The proposed HT has stealthiness and general applicability.

关键词： hardware Trojan horses

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WiderFrame: An Automatic Customization Framework for Building CNN Accelerators on FPGAs: Work-in-Progress

WiderFrame: An Automatic Customization Framework for Buildin...

引用

international conference on hardware/software codesign and system synthesis (codes+isss)

作者： Gong, Lei Wang, Chao Li, Xi Zhou, Xuehai Univ Sci & Technol China Sch Comp Sci & Technol Hefei Peoples R China

ISBN: (纸本)9781728191980

hardware acceleration based on FPGA has been an important means to improve the computational efficiency of CNNs. However, due to the increasing complexity of the modern CNNs and the diversity of neural computing engines, it is challenging to make full use of FPGAs' customizability for efficient and fast accelerator designs. This paper proposes Wider-Frame, an automatic customization framework for building CNN accelerators on FPGA. Towards fully exploiting the customizability of FPGA for specific computing scenarios, WiderFrame integrates a systematical design space exploration methodology considered with different parallel and data reuse manners among various neural computing engines, a parameterized configurable code template with a set of macro instruction mechanism, for automatically generating the underlying hardware units and the control flow. Evaluation results show that WiderFrame can well support more CNN types, and can improve the performance and the energy efficiency up to 1.25x and 1.68x compared with state-of-the-art frameworks.

关键词： FPGA CNN hardware accelerator Framework

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Work-in-Progress: A concept of a hardware design environment with the functional language Elixir

Work-in-Progress: A concept of a hardware design environment...

引用

Embedded systems Week / Int Conf on Compilers, Architecture, and synthesis for Embedded systems (CASES) / international conference on hardware/software codesign and system synthesis (codes+isss) / Int Conf on Embedded software (EMSOFT)

作者： Takase, Hideki Matsui, Kentaro Ueno, Yoshihiro Mori, Masakazu Hisae, Yuki Yamazaki, Susumu Kyoto Univ Sakyo Ku Kyoto Japan Delight Syst Co Ltd Chuo Ku Fukuoka Japan Karabiner Technol Inc Chuo Ku Fukuoka Japan Univ Kitakyushu Wakamatsu Ku Kitakushu Japan JST PRESTO Tokyo Japan

ISBN: (纸本)9781450369237

The functional language Elixir is designed to be effective for the application. One of the most considerable feature of Elixir is that it is easy to realize the parallel processing with the standard library, such as Flow. In this paper, we study a design environment for hardware circuits using Elixir as a design language. We propose a synthesize flow for data flow hardware on the FPGA from the native Elixir code. Our method synthesizes functional equivalence circuits from the description of Enum and Flow in Elixir, which are libraries for direct manipulation and parallel processing of data collection in Elixir. Data flow is implemented base on the pipeline operator vertical bar> which connects the processing relation of the function by the data processing order. To realize a hardware design environment by Elixir, this paper shares current status of our implementation.

关键词： Elixir functional language high-level synthesis

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Formal Verification of GCSE in the Scheduling of High-level synthesis: Work-in-Progress

Formal Verification of GCSE in the Scheduling of High-level ...

引用

international conference on hardware/software codesign and system synthesis (codes)

作者： Jian Hu Yongyang Hu Long Yu Wentao Wang Haitao Yang Yun Kang Jie Cheng The Sixty-third Research Institute National University of Defense Technology NanJing China College of Computer Science and Technology National University of Defense Technology ChangSha China

ISBN: (数字)9781728191980

ISBN: (纸本)9781728191997

High-level synthesis entails application of a sequence of transformations to compile a high-level description of a hardware design (e.g., in C/C++/systemC) into a register-transfer level (RTL) implementation. However, an error may exist in the RTL implementation from the compiler in the high-level synthesis due to the complex and error prone compiling process. Global common subexpression elimination (GCSE) is a commonly used code motion technique in the scheduling of high-level synthesis. In this paper, we present an equivalence checking method to verify GCSE in the scheduling of high-level synthesis by enhancing the path equivalence criteria. The initial experimental results demonstrate our method can indeed verify the GCSE which has not been properly addressed in the past.

关键词： hardware Formal verification

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Heatmap-Aware Low-Cost Design to Resist Adversarial Attacks: Work-in-Progress

Heatmap-Aware Low-Cost Design to Resist Adversarial Attacks:...

引用

international conference on hardware/software codesign and system synthesis (codes)

作者： Zhiyuan He Wei Jiang Jinyu Zhan Xupeng Wang Xiangyu Wen School of Information & Software Engineering University of Electronic Science & Technology of China China

ISBN: (数字)9781728191980

ISBN: (纸本)9781728191997

It is a challenging task to resist adversarial attacks due to the imperceptibility of adversarial examples. The passive defense method is developed based on a series of input transformations and has achieved a promising result, which however suffers from a high computation cost. In this paper, we design a new heatmap-aware method to defend adversarial attacks, leading to a significant decrease in the time cost. To be specific, we compute the classification importance from each part of the input to obtain the heatmap of the data, and the key areas of classification are extracted according to the heatmap. A series of transformations are applied to the key areas of the classification, which reduces the amount of data to be processed and thus reduces the time cost. A set of preliminary experiments are conducted to testify the effectiveness of the proposed approach.

关键词： Heating systems Resists Data mining Task analysis

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Model Stealing Defense with Hybrid Fuzzy Models: Work-in-Progress

Model Stealing Defense with Hybrid Fuzzy Models: Work-in-Pro...

引用

international conference on hardware/software codesign and system synthesis (codes)

作者： Zicheng Gong Wei Jiang Jinyu Zhan Ziwei Song School of Information & Software Engineering University of Electronic Science & Technology of China China

ISBN: (数字)9781728191980

ISBN: (纸本)9781728191997

With increasing applications of Deep Neural Networks (DNNs) to edge computing systems, security issues have received more attentions. Particularly, model stealing attack is one of the biggest challenge to the privacy of models. To defend against model stealing attack, we propose a novel protection architecture with fuzzy models. Each fuzzy model is designed to generate wrong predictions corresponding to a particular category. In addition' we design a special voting strategy to eliminate the systemic errors, which can destroy the dark knowledge in predictions at the same time. Preliminary experiments show that our method substantially decreases the clone model's accuracy (up to 20%) without loss of inference accuracy for benign users.

关键词： Privacy Computational modeling Neural networks Computer architecture Predictive models Security Edge computing

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Meta-Chain: User-Aware Cross-Layer Space Allocation Strategy for Blockchain Storage systems: Work-in-Progress

Meta-Chain: User-Aware Cross-Layer Space Allocation Strategy...

引用

international conference on hardware/software codesign and system synthesis (codes)

作者： Jing Liao Zhengda Li Yi Wang College of Computer Science and Software Engineering The National Engineering Laboratory for Big Data System Computing Technology Shenzhen University Shenzhen China

ISBN: (数字)9781728191980

ISBN: (纸本)9781728191997

Current LSM-Tree-based blockchain storage system will assign the data from multiple system users to the same disk drive. This will lead to the inefficient usage of physical spaces in disk and cause extra compaction operations for LSM - Tree. This paper presents Meta-Chain , a user-aware cross-layer space allocation strategy for blockchain storage systems. As a cross-layer design, Meta-Chain redesigns the organization of LSM - Tree and utilizes the rich functionalities provided by open-channel SSD. Experimental results show that Meta-Chain can effectively reduce write amplification and extend the lifetime of SSD in comparison with representative schemes.

关键词： Disk drives Blockchain Organizations Compaction Resource management

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Accelerating Queries of MongoDB by an FPGA-based Storage Engine: Work-in-Progress

Accelerating Queries of MongoDB by an FPGA-based Storage Eng...

引用

international conference on hardware/software codesign and system synthesis (codes)

作者： Jinyu Zhan Junting Wu Wei Jiang Ying Li Jianping Zhu School of Information & Software Engineering University of Electronic Science & Technology of China China Tencent Technology Shenzhen Company Ltd China

ISBN: (数字)9781728191980

ISBN: (纸本)9781728191997

In this paper, we propose a storage engine for MongoDB to accelerate the queries and reduce the memory usage. An FPGA-based query accelerator is deployed to speed up the queries while hot data is migrated from memory to SSD to reduce memory occupancy by our storage engine. Moreover, multiple query tasks of MongoDB are performed in parallel and query conditions are parameterized to support diversified queries. Based on TPC- H benchmark and Tencent data set, experimental results demonstrate that our storage engine can achieve higher query efficiency (saving up to 63.5 % time overhead) and lower memory occupancy (reducing up to 73.4 % memory usage) compared with traditional MongoDB.

关键词： Memory management Benchmark testing Acceleration Task analysis Engines Field programmable gate arrays

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Work-in-Progress: PowerMonitor: Design Pattern for Modelling Energy-Aware Embedded systems

Work-in-Progress: PowerMonitor: Design Pattern for Modelling...

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作者： Uelschen, Michael Schaarschmidt, Marco Fuhrmann, Christian Westerkamp, Clemens Univ Appl Sci Osnabruck Fac Engn & Comp Sci Osnabruck Germany

ISBN: (纸本)9781450369244

This paper introduces a new software design pattern that can be applied to embedded systems. The pattern enables the application to access the peripheral devices under defined power conditions and allows to implement a fine-grained and energy-efficient strategy on using functional units of the microcontroller. The approach considers power consumption properties of the CPU itself as well as properties of external peripheral devices like connected sensors and actuators.

关键词： software Architecture Design Patterns Embedded systems Energy efficiency Template Meta Programming

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