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international conference on hardware/software codesign and system synthesis, codes+isss 2015

ISBN: (纸本)9781467383219

The proceedings contain 24 papers. The topics discussed include: how to improve the space utilization of Dedup-based PCM storage devices?;a tiny-capacitor-backed non-volatile buffer to reduce storage writes in smartphones;lightweight virtual memory support for many-core accelerators in heterogeneous embedded SoCs;improved hard real-time scheduling of CSDF-modeled streaming applications;hardware synthesis from a recursive functional language;power-awareness and smart-resource management in embedded computing systems;an online wear state monitoring methodology for off-the-shelf embedded processors;big/little deep neural network for ultra low power inference;an approximate compressor for wearable biomedical healthcare monitoring systems;and fast parallel application and multiprocessor design space exploration from sequential code.

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An Energy-aware Spiking Neural Network hardware Mapping based on Particle Swarm Optimization and Genetic Algorithm

An Energy-aware Spiking Neural Network Hardware Mapping base...

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international conference on hardware/software codesign and system synthesis (codes)

作者： Junxiu Liu Xingyue Huang Dong Jiang Yuling Luo School of Electronic Engineering Guangxi Normal University Guilin China

ISBN: (数字)9781728191980

ISBN: (纸本)9781728191997

Spiking Neuron Network (SNN) is a biological neural network model which shows great capability in the time series data processing and pattern recognition etc. according to the recent research. It has been implemented in hardware system with a good scalability, where the Networks-on-Chip (NoC) interconnection strategy is widely used for the data communications between the neurons. The mapping between a SNN and a NoC hardware system is one of the challenge for the development of the hardware SNNs. In this paper, a hybrid Particle Swarm Optimization (PSO) algorithm for hardware SNN mapping is proposed with the object of minimizing the energy consumption. Compared to the conventional PSO, it can search the mapping solutions through three directions which can speed up the finding. In the meantime, the Genetic Algorithm (GA) is combined to provide the mutation operation to avoid converging to the local optimum. A typical hardware SNN is used as the testbench and results show that an effective hardware SNN mapping is obtained with a low energy consumption, and local optimum is avoided compared to other approaches.

关键词： Energy consumption Neurons Time series analysis hardware Particle swarm optimization Biological neural networks Genetic algorithms

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RePAiR: A Strategy for Reducing Peak Temperature while Maximising Accuracy of Approximate Real-Time Computing: Work-in-Progress

RePAiR: A Strategy for Reducing Peak Temperature while Maxim...

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international conference on hardware/software codesign and system synthesis (codes)

作者： Shounak Chakraborty Sangeet Saha Magnus Sjalander Klaus McDonald-Maier Norwegian University of Science and Technology (NTNU) Trondheim Norway Embedded and Intelligent Systems Laboratory University of Essex Colchetser UK

ISBN: (数字)9781728191980

ISBN: (纸本)9781728191997

Improving accuracy in approximate real-time computing without violating thermal-energy constraints of the underlying hardware is a challenging problem. The execution of approximate real-time tasks can individually be bifurcated into two components: (i) execution of the mandatory part of the task to obtain a result of acceptable quality, followed by (ii) partial/complete execution of the optional part, which refines the initially obtained result, to increase the accuracy without violating the temporal-deadline. This paper introduces RePAiR, a novel task-allocation strategy for approximate real-time applications, combined with fine-grained DVFS and on-line task migration of the cores and power-gating of the last level cache, to reduce chip-temperature while respecting both deadline and thermal constraints. Furthermore, gained thermal benefits can be traded against system-level accuracy by extending the execution-time of the optional part.

关键词： Maintenance engineering Real-time systems hardware Task analysis

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An ESL Methodology for HW/SW Co-Design of Monitorable Embedded systems: the “Design for Monitorability” Project - Work-in-Progress

An ESL Methodology for HW/SW Co-Design of Monitorable Embedd...

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international conference on hardware/software codesign and system synthesis (codes)

作者： Giacomo Valente Tania Di Mascio Luigi Pomante Vincenzo Stoico DISIM/DEWS Università degli Studi dell'Aquila ITALY

ISBN: (数字)9781728191980

ISBN: (纸本)9781728191997

This paper proposes an Electronic system-Level (ESL) Methodology for HW/SW Co-Design of Monitorable Embedded systems. In particular, this paper aims to define an innovative topic called Design for Monitorability (DfM). DfM exploits ESL HW/SW co-design techniques to satisfy Monitorability Requirements (M_REQs) by considering them since the initial steps of the HW/SW co-design flow as additional ones. DfM has the final goal of suggesting to the designer an On-Chip Monitoring system (OCMS) able to satisfy M _ REQs., to be integrated in the final system (i.e., possibly heterogeneous and/or parallel SoCs) while still respecting the other possible nonfunctional requirements imposed to the system implementation (e.g., execution time, area/resource utilization, energy consumption, etc.). The description of the motivations and the main concepts behind the proposed methodology represent the core of the paper.

关键词： Energy consumption Embedded systems system-on-chip Monitoring system implementation

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A Fast Design Space Exploration Framework for the Deep Learning Accelerators: Work-in-Progress

A Fast Design Space Exploration Framework for the Deep Learn...

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international conference on hardware/software codesign and system synthesis (codes+isss)

作者： Colucci, Alessio Marchisio, Alberto Bussolino, Beatrice Mrazek, Voitech Martina, Maurizio Masera, Guido Shafique, Muhammad Tech Univ Wien Vienna Austria Politecn Torino Turin Italy Brno Univ Technol Fac Informat Technol IT4Innovat Ctr Excellence Brno Czech Republic New York Univ Abu Dhabi Div Engn Abu Dhabi U Arab Emirates

ISBN: (纸本)9781728191980

The Capsule Networks (CapsNets) is an advanced form of Convolutional Neural Network (CNN), capable of learning spatial relations and being invariant to transformations. CapsNets requires complex matrix operations which current accelerators are not optimized for, concerning both training and inference passes. Current state-of-the-art simulators and design space exploration (DSE) tools for DNN hardware neglect the modeling of training operations, while requiring long exploration times that slow down the complete design flow. These impediments restrict the real-world applications of CapsNets (e.g., autonomous driving and robotics) as well as the further development of DNNs in life-long learning scenarios that require training on low-power embedded devices. Towards this, we present XploreDL, a novel framework to perform fast yet high-fidelity USE for both inference and training accelerators, supporting both CNNs and CapsNets operations. XploreDL enables a resource-efficient DSE for accelerators, focusing on power, area, and latency, highlighting Pareto-optimal solutions which can be a green-lit to expedite the design flow. XploreDL can reach the same fidelity as ARM's SCALE-sim, while providing 600x speedup and having a 50x lower memory-footprint. Preliminary results with a deep CapsNet model on MNIST for training accelerators show promising Pareto-optimal architectures with up to 0.4 TOPS/squared-nun and 800 fJ/op efficiency. With inference accelerators for AlexNet the Pareto-optimal solutions reach up to 1.8 TOPS/squared-mm and 200 fJ/op efficiency.

关键词： Design Space Exploration hardware Accelerator Capsule Networks Convolutional Neural Networks Training

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WiderFrame: An Automatic Customization Framework for Building CNN Accelerators on FPGAs: Work-in-Progress

WiderFrame: An Automatic Customization Framework for Buildin...

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international conference on hardware/software codesign and system synthesis (codes)

作者： Lei Gong Chao Wang Xi Li Xuehai Zhou School of Computer Science and Technology University of Science and Technology of China

ISBN: (数字)9781728191980

ISBN: (纸本)9781728191997

hardware acceleration based on FPGA has been an important means to improve the computational efficiency of CNNs. However, due to the increasing complexity of the modern CNNs and the diversity of neural computing engines, it is challenging to make full use of FPGAs' customizability for efficient and fast accelerator designs. This paper proposes Wider-Frame, an automatic customization framework for building CNN accelerators on FPGA. Towards fully exploiting the customiz-ability of FPGA for specific computing scenarios, WiderFrame integrates a systematical design space exploration methodology considered with different parallel and data reuse manners among various neural computing engines, a parameterized configurable code template with a set of macro instruction mechanism, for automatically generating the underlying hardware units and the control flow. Evaluation results show that WiderFrame can well support more CNN types, and can improve the performance and the energy efficiency up to 1.25 x and 1.68 x compared with state-of-the-art frameworks.

关键词： Design methodology Buildings Energy efficiency Space exploration Field programmable gate arrays Engines hardware acceleration

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HW-FlowQ: A Multi-Abstraction Level HW-CNN Co-design Quantization Methodology

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ACM TRANSACTIONS ON EMBEDDED COMPUTING systemS 2021年第5期20卷 66-66页

作者： Fasfous, Nael Vemparala, Manoj Rohit Frickenstein, Alexander Valpreda, Emanuele Salihu, Driton Nguyen Anh Vu Doan Unger, Christian Nagaraja, Naveen Shankar Martina, Maurizio Stechele, Walter Tech Univ Munich Munich Germany BMW Autonomous Driving Munich Germany Politecn Torino Turin Italy

Model compression through quantization is commonly applied to convolutional neural networks (CNNs) deployed on compute and memory-constrained embedded platforms. Different layers of the CNN can have varying degrees of numerical precision for both weights and activations, resulting in a large search space. Together with the hardware (HW) design space, the challenge of finding the globally optimal HW-CNN combination for a given application becomes daunting. To this end, we propose HW-FlowQ, a systematic approach that enables the co-design of the target hardware platform and the compressed CNN model through quantization. The search space is viewed at three levels of abstraction, allowing for an iterative approach for narrowing down the solution space before reaching a high-fidelity CNN hardware modeling tool, capable of capturing the effects of mixed-precision quantization strategies on different hardware architectures (processing unit counts, memory levels, cost models, dataflows) and two types of computation engines (bit-parallel vectorized, bit-serial). To combine both worlds, a multi-objective non-dominated sorting genetic algorithm (NSGA-II) is leveraged to establish a Pareto-optimal set of quantization strategies for the target HW-metrics at each abstraction level. HW-FlowQ detects optima in a discrete search space and maximizes the task-related accuracy of the underlying CNN while minimizing hardware-related costs. The Pareto-front approach keeps the design space open to a range of non-dominated solutions before refining the design to a more detailed level of abstraction. With equivalent prediction accuracy, we improve the energy and latency by 20% and 45% respectively for ResNet56 compared to existing mixed-precision search methods.

关键词： Convolutional neural networks multi-objective optimization hardware modeling genetic algorithms quantization

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Aggressive Energy Reduction for Video Inference with software-only Strategies

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ACM TRANSACTIONS ON EMBEDDED COMPUTING systemS 2019年第5期18卷 1–20页

作者： Goncalves, Larissa Rozales De Moura, Rafael Fao Carro, Luigi Univ Fed Rio Grande do Sul Porto Alegre RS Brazil

In the past years, several works have proposed custom hardware and software-based techniques for the acceleration of Convolutional Neural Networks (CNNs). Most of these works focus on saving computations by changing the used precision or modifying frame processing. To reach a more aggressive energy reduction, in this paper we propose software-only modifications to the CNNs inference process. Our approach exploits the inherent locality in videos by replacing entire frame computations with a movement prediction algorithm. Furthermore, when a frame must be processed, we avoid energy-demanding floating-point operations, and at the same time reduce memory accesses by employing look-up tables in place of the original convolutions. Using the proposed approach, one can reach significant energy gains of more than 25x for security cameras, and 12x for moving vehicles applications, with only small software modifications.

关键词： Convolutional Neural Networks frame predicton computation reuse

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Work-in-Progress: A Neuromorphic Approach of the Sound Source Localization Task in Real-Time Embedded systems

Work-in-Progress: A Neuromorphic Approach of the Sound Sourc...

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Embedded systems Week / Int Conf on Compilers, Architecture, and synthesis for Embedded systems (CASES) / international conference on hardware/software codesign and system synthesis (codes+isss) / Int Conf on Embedded software (EMSOFT)

作者： Gutierrez-Galan, Daniel Pedro Jimenez-Fernandez, Juan Jimenez-Fernandez, Angel Tapiador-Morales, Ricardo Rios-Navarro, Antonio Linares-Barranco, Alejandro Univ Seville Seville Spain

ISBN: (纸本)9781450369244

Autonomous robots have become a very popular topic within the artificial intelligence field. These systems are able to perform difficult or risky tasks that could be dangerous when done by humans or trained animals. Vision is commonly considered the most relevant input sensor for autonomous robots and tracking systems. However, auditory information is also important in some specific situations where vision cannot provide any useful information when navigating. In this work, a spike-based model of the medial superior olive of the inner ear has been implemented in reconfigurable hardware for performing sound source localization in real time. Future works will focus on integrating this information with vision in order to achieve a fully bio-inspired autonomous tracking system.

关键词： Neuromorphic auditory sensor FPGA binaural sound localization real-time audio processing spike-based system

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FLASH: Fast Neural Architecture Search with hardware Optimization

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ACM TRANSACTIONS ON EMBEDDED COMPUTING systemS 2021年第5期20卷 63-63页

作者： Li, Guihong Mandal, Sumit K. Ogras, Umit Y. Marculescu, Radu Univ Texas Austin Austin TX 78712 USA Univ Wisconsin Madison WI USA

Neural architecture search (NAS) is a promising technique to design efficient and high-performance deep neural networks (DNNs). As the performance requirements of ML applications grow continuously, the hardware accelerators start playing a central role in DNN design. This trend makes NAS even more complicated and time-consuming for most real applications. This paper proposes FLASH, a very fast NAS methodology that co-optimizes the DNN accuracy and performance on a real hardware platform. As the main theoretical contribution, we first propose the NN-Degree, an analytical metric to quantify the topological characteristics of DNNs with skip connections (e.g., DenseNets, ResNets, Wide-ResNets, and MobileNets). The newly proposed NN-Degree allows us to do training-free NAS within one second and build an accuracy predictor by training as few as 25 samples out of a vast search space with more than 63 billion configurations. Second, by performing inference on the target hardware, we fine-tune and validate our analytical models to estimate the latency, area, and energy consumption of various DNN architectures while executing standard ML datasets. Third, we construct a hierarchical algorithm based on simplicial homology global optimization (SHGO) to optimize the model-architecture co-design process, while considering the area, latency, and energy consumption of the target hardware. We demonstrate that, compared to the state-of-the-art NAS approaches, our proposed hierarchical SHGO-based algorithm enables more than four orders of magnitude speedup (specifically, the execution time of the proposed algorithm is about 0.1 seconds). Finally, our experimental evaluations show that FLASH is easily transferable to different hardware architectures, thus enabling us to do NAS on a Raspberry Pi-3B processor in less than 3 seconds.

关键词： Neural networks network science hardware optimization neural architecture search model-architecture co-design resource-constrained devices

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