检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

769 篇 会议
32 篇 期刊文献

馆藏范围

801 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

561 篇 工学
- 502 篇 计算机科学与技术...
- 285 篇 软件工程
- 224 篇 电子科学与技术（可...
- 161 篇 电气工程
- 87 篇 信息与通信工程
- 47 篇 控制科学与工程
- 34 篇 动力工程及工程热...
- 25 篇 机械工程
- 16 篇 生物工程
- 13 篇 仪器科学与技术
- 10 篇 材料科学与工程（可...
- 9 篇 建筑学
- 9 篇 土木工程
- 9 篇 化学工程与技术
- 8 篇 生物医学工程（可授...
- 7 篇 冶金工程
- 5 篇 光学工程
- 3 篇 核科学与技术
- 3 篇 农业工程
201 篇 理学
- 165 篇 数学
- 37 篇 物理学
- 19 篇 统计学（可授理学、...
- 17 篇 生物学
- 8 篇 化学
- 8 篇 系统科学
55 篇 管理学
- 47 篇 管理科学与工程(可...
- 30 篇 工商管理
- 9 篇 图书情报与档案管...
14 篇 经济学
- 14 篇 应用经济学
10 篇 法学
- 8 篇 社会学
3 篇 农学
3 篇 医学
2 篇 教育学

主题

426 篇 field programmab...
220 篇 field programmab...
72 篇 hardware
40 篇 computer archite...
29 篇 clocks
27 篇 software
27 篇 fpga
24 篇 routing
21 篇 table lookup
19 篇 acceleration
18 篇 random access me...
17 篇 computational mo...
17 篇 real-time system...
16 篇 logic gates
14 篇 registers
13 篇 delays
13 篇 throughput
13 篇 switches
13 篇 kernel
13 篇 digital signal p...

机构

7 篇 univ of toronto ...
6 篇 school of comput...
6 篇 univ of toronto
5 篇 university of to...
5 篇 univ of californ...
5 篇 altera corporati...
5 篇 intel corporatio...
4 篇 univ british col...
4 篇 department of el...
4 篇 dept. of cs 256-...
4 篇 department of el...
3 篇 computer science...
3 篇 tsinghua univers...
3 篇 department of ee...
3 篇 xilinx inc. san ...
3 篇 politecn milan d...
3 篇 fudan univ state...
3 篇 northwestern uni...
3 篇 state key lab of...
3 篇 nanyang technolo...

作者

22 篇 rose jonathan
19 篇 cong jason
12 篇 betz vaughn
10 篇 wawrzynek john
10 篇 chen deming
9 篇 dehon andré
9 篇 hauck scott
9 篇 zhang zhiru
8 篇 chow paul
7 篇 wilton steven j....
7 篇 schmit herman
7 篇 constantinides g...
7 篇 langhammer marti...
6 篇 cheung peter y. ...
6 篇 wilton steven j....
6 篇 pasca bogdan
6 篇 santambrogio mar...
6 篇 li fei
6 篇 prasanna viktor ...
6 篇 he lei

语言

795 篇 英文
6 篇 其他

检索条件"任意字段=2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA 2016"

共 801 条记录，以下是101-110 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

Fast routability-driven router for fpgas

Fast routability-driven router for FPGAs

引用

Proceedings of the 1998 acm/sigda 6th international symposium on field programmable gate arrays, fpga

作者： Swartz, Jordan S. Betz, Vaughn Rose, Jonathan Univ of Toronto Toronto Canada

Three factors are driving the demand for rapid field programmable gate array (fpga) compilation. First, as fpgas grown in logic capacity, the compile computation grows more quickly than the compute power of the available computers. Second, there exists a subset of users who are willing to pay for very high speed compile with a decrease in quality of result. Third, very high speed compile is a long-standing desire of those using fpga-based custom computing machines, as they want compile times at least closer to those of regular computers. A routing algorithm and routing tool that relates these three unique capabilities to very high-speed compile is presented.

关键词： field programmable gate arrays

来源：评论

学校读者我要写书评

暂无评论

Architecture adaptive routability-driven placement for fpgas

Architecture adaptive routability-driven placement for FPGAs

引用

acm/sigda Thirteenth acm international symposium on field programmable gate arrays - fpga 2005

作者： Sharma, Akshay Ebeling, Carl Hauck, Scott Electrical Engineering University of Washington Seattle WA Computer Science and Engineering University of Washington Seattle WA

Current fpga placement algorithms estimate the routability of a placement using architecture-specific metrics. The shortcoming of using architecture-specific routability estimates is limited adaptability. A placement algorithm that is targeted to a class of architecturally similar fpgas may not be easily adapted to other architectures. The subject of this paper is the development of a routability-driven architecture adaptive fpga placement algorithm called Independence. The core of the Independence algorithm is a simultaneous place-and-route approach that tightly couples a simulated annealing placement algorithm with an architecture adaptive fpga router (Pathfinder). The results of our experiments demonstrate Independence's adaptability to island-style and hierarchical fpga architectures. The quality of the placements produced by Independence is within 5% of the quality of VPR's placements and 17% better than the placements produced by HSRA's place-and-route tool. Further, our results show that Independence produces clearly superior placements on routing-poor island-style fpga architectures.

关键词： field programmable gate arrays

来源：评论

学校读者我要写书评

暂无评论

A new universal test pattern auto-generating approach for fpga logic resources

A new universal test pattern auto-generating approach for FP...

引用

acm/sigda Thirteenth acm international symposium on field programmable gate arrays - fpga 2005

作者： OuYang, Yirong Tong, Jiarong State Key Lab of ASIC and System Fudan University Shanghai China

This paper presents a new universal test approach for fpga logic resources. It includes a new greedy configuration-generating algorithm, and a new fpga Configurable Logic Block (CLB) test model. The model is based on two directed graphs: a structure graph and a configuration graph, which convey the important information from the CLB gate level circuit to the greedy configuration- generating algorithm, so the algorithm can generate minimum the number of test configurations to achieve a given fault coverage. With this new approach, researchers can easily get test patterns optimized both in test time and fault coverage for different fpga architectures. At the end, we compare experiment results with other test approaches, and the results show test pattern from the new approach is even more efficient than pattern from manual optimization. It also proves that the approach can deal with different types of fpgas very well.

关键词： field programmable gate arrays

来源：评论

学校读者我要写书评

暂无评论

Soft error rate estimation and mitigation for SRAM-based fpgas 05

Soft error rate estimation and mitigation for SRAM-based FPG...

引用

acm/sigda Thirteenth acm international symposium on field programmable gate arrays - fpga 2005

作者： Asadi, Ghazanfar Tahoori, Mehdi B. Northeastern University Dept. of Electrical and Computer Engineering Boston MA 02115 United States

ISBN: (纸本)9781595930293

fpga-based designs are more susceptible to single-event upsets (SEUs) compared to ASIC designs. Soft error rate (SER) estimation is a crucial step in the design of soft error tolerant schemes to balance reliability, performance, and cost of the system. Previous techniques on fpga SER estimation are based on time-consuming fault injection and simulation methods. In this paper, we present an analytical approach to estimate the failure rate of designs mapped into fpgas. Experimental results show that this technique is orders of magnitude faster than fault injection method while is very accurate. We also present a high-reliable low-cost mitigation technique which can significantly improve the availability of fpga-based designs. This technique is able to tolerate SEUs in both user and configuration bits of mapped designs. Copyright 2005 acm.

关键词： field programmable gate arrays

来源：评论

学校读者我要写书评

暂无评论

Technology mapping issues for an fpga with lookup tables and PLA-like blocks 00

Technology mapping issues for an FPGA with lookup tables and...

引用

fpga 2000: acm/sigda international symposium on field programmable gate arrays

作者： Kaviani, Alireza Brown, Stephen Xilinx Inc San Jose CA United States

ISBN: (纸本)9781581131932

In this paper we present new technology mapping algorithms for use in a programmable logic device (PLD) that contains both lookup tables (LUTs) and PLA-like blocks. The technology mapping algorithms partially collapse circuits to reduce either area or depth, and pack the circuits into a minimum number of LUTs and PLA-like blocks. Since no other technology mapping algorithm for this problem has been previously published, we cannot compare our approach to others. Instead, to illustrate the importance of this problem we use our algorithms to investigate the benefits provided by a PLD architecture with both LUTs and PLA-like blocks compared to a traditional LUT-based fpga. The experimental results indicate that our mixed PLD architecture is more area-efficient than LUT-based fpgas by up to 29%, or more depth-efficient by up to 75%.

关键词： field programmable gate arrays

来源：评论

学校读者我要写书评

暂无评论

PERG-Rx: A hardware pattern-matching engine limited regular expressions

PERG-Rx: A hardware pattern-matching engine limited regular ...

引用

7th acm sigda international symposium on field-programmable gate arrays, fpga'09

作者： Ho, Johnny Tsung Lin Lemieux, Guy G.F. University of British Columbia Canada

ISBN: (纸本)9781605584102

PERG is a pattern matching engine designed for locating predefined byte string patterns (rules) from ClamAV virus signature database in a data stream. This paper presents PERG-Rx, an extension of PERG that adds limited regular expression support for wildcard patterns used by rules that represent polymorphic viruses. To reduce the amount of state needed to track so many regular expressions, PERG-Rx employs a lossy scheme which increases the rate of false positives detected as the required state grows. The scalability and dynamic updatability of the PERG-Rx architecture to database updates are also evaluated. Copyright 2009 acm.

关键词： field programmable gate arrays (fpga)

来源：评论

学校读者我要写书评

暂无评论

Design of fpga interconnect for multilevel metalization

Design of FPGA interconnect for multilevel metalization

引用

acm/sigda 11th acm international symposium on field programmable gate arrays

作者： Rubin, Raphael DeHon, Andreá Dept. of CS 256-80 California Institute of Technology Pasadena CA 91125 United States

How does multilevel metalization impact the design of fpga interconnect? The availability of a growing number of metal layers presents the opportunity to use wiring in the third-dimension to reduce switch requirements. Unfortunately, traditional fpga wiring schemes are not designed to exploit these additional metal layers. We introduce an alternate topology, based on Leighton's Mesh-of-Trees, which carefully exploits hierarchy to allow additional metal layers to support arbitrary device scaling. When wiring layers grow sufficiently fast with aggregate network size (N), our network requires only O(N) area: this is in stark contrast to traditional. Manhattan fpga routing schemes where switching requirements alone grow superlinearly in N. In practice, we show that, even for the admittedly small designs in the Toronto "fpga Place and Route Challenge," the Mesh-of-Trees networks require 10% less switches than the standard, Manhattan fpga routing scheme.

关键词： field programmable gate arrays

来源：评论

学校读者我要写书评

暂无评论

Network-on-Chip programmable Platform in Versal™ ACAP Architecture

Network-on-Chip Programmable Platform in Versal™ ACAP Archi...

引用

acm/sigda international symposium on field-programmable gate arrays (fpga)

作者： Swarbrick, Ian Gaitonde, Dinesh Ahmad, Sagheer Gaide, Brian Arbel, Ygal Xilinx Inc San Jose CA 95124 USA

ISBN: (纸本)9781450361378

This paper outlines the Network-on-Chip (NoC) on Xilinx's next generation Versal (TM) architecture. It is a hardened NoC that is present in Xilinx's next-generation 7nm architecture devices. These devices include many other new hardened features that make up the Adaptable Computing Acceleration Platform (ACAP) devices. There is a trend in fpga devices of hardening many commonly used components such as processors, memory controllers and other IO controllers. The next generation of Xilinx devices take this a step further by providing a device-global memory mapped NoC which connects these components and the fabric in an integrated fashion. The NoC unifies communication between the processor system, fpga fabric, memory subsystem and other hardened accelerator functions. This paper gives an overview of the Versal architecture NoC. It also motivates some of the specific characteristics of the architecture. We show how hardening the NoC lets users quickly implement high performance system level interconnect.

关键词： ACAP Versal fpga Stacked Silicon SSIT Adaptable Compute Acceleration Platform NoC fpga Architecture fpga CAD Xilinx

来源：评论

学校读者我要写书评

暂无评论

Intra-Masking Dual-Rail Memory on LUT Implementation for Tamper-Resistant AES on fpga 12

Intra-Masking Dual-Rail Memory on LUT Implementation for Tam...

引用

20th acm/sigda international symposium on field-programmable gate arrays (fpga)

作者： Hoang, Anh-Tuan Fujino, Takeshi Ritsumeikan Univ Kusatsu Shiga 5258577 Japan

ISBN: (纸本)9781450311557

In current countermeasure design trends against differential power analysis (DPA), security at gate level is required in addition to the security algorithm. Several dual-rail pre-charge logics (DPL) have been proposed to achieve this goal. Designs using ASIC can attain this goal owing to its backend design restrictions on placement and routing. However, implementing these designs on field programmable gate arrays (fpga) without information leakage is still a problem because of the difficulty involved in the restrictions on placement and routing on fpga. This paper describes our novel masked dual-rail pre-charged memory approach, called "intra-masking dual-rail memory on LUT," and its implementation on fpga for tamper-resistant AES. In the proposed design, all unsafe nodes, such as unmasking and masking, and the dual-rail memory and buses are packed into a single LUT. This makes them balanced and independent of the placement and routing tools. The design is independent of the cryptographic algorithm, and hence, it can be applied to available cryptographic standards such as DES or AES as well as future standards. It requires no special placement or route constraints in its implementation. A correlation power analysis (CPA) attack on 1,000,000 traces of AES implementation on fpga showed that the secret information is well protected against first-order side-channel attacks. Even though the number of LUTs used for memory in this implementation is seven times greater than that of the conventional unprotected single-rail memory table-lookup AES and three times greater than the implementation based on a composite field, it requires a smaller number of LUTs than all other advanced tamper-resistant implementations such as the wave dynamic differential logic, masked dual-rail pre-charge logic, and threshold.

关键词： Side-Channel Attack Differential Power Analysis (DPA) Masking Dual-Rail Memory Intra-Masking Dual-Rail Memory on LUT Tamper Resistance AES field programmable gate Array (fpga)

来源：评论

学校读者我要写书评

暂无评论

Leveraging latency-insensitivity to ease multiple fpga design 12

Leveraging latency-insensitivity to ease multiple FPGA desig...

引用

2012 acm/sigda international symposium on field programmable gate arrays, fpga'12

作者： Fleming, Kermin Elliott Adler, Michael Pellauer, Michael Parashar, Angshuman Mithal, Arvind Emer, Joel Intel Corporation VSSAD Group Hudson MA United States Massachusetts Institute of Technology Computer Science and A.I. Laboratory Cambridge MA United States

ISBN: (纸本)9781450311557

Traditionally, hardware designs partitioned across multiple fpgas have had low performance due to the inefficiency of maintaining cycle-by-cycle timing among discrete fpgas. In this paper, we present a mechanism by which complex designs may be efficiently and automatically partitioned among multiple fpgas using explicitly programmed latency-insensitive links. We describe the automatic synthesis of an area efficient, high performance network for routing these inter-fpga links. By mapping a diverse set of large research prototypes onto a multiple fpga platform, we demonstrate that our tool obtains significant gains in design feasibility, compilation time, and even wall-clock performance. © 2012 acm.

关键词： field programmable gate arrays (fpga)

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共81页 << < 7 8 9 10 11 12 13 14 15 16 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：