检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

769 篇 会议
32 篇 期刊文献

馆藏范围

801 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

561 篇 工学
- 502 篇 计算机科学与技术...
- 285 篇 软件工程
- 224 篇 电子科学与技术（可...
- 161 篇 电气工程
- 87 篇 信息与通信工程
- 47 篇 控制科学与工程
- 34 篇 动力工程及工程热...
- 25 篇 机械工程
- 16 篇 生物工程
- 13 篇 仪器科学与技术
- 10 篇 材料科学与工程（可...
- 9 篇 建筑学
- 9 篇 土木工程
- 9 篇 化学工程与技术
- 8 篇 生物医学工程（可授...
- 7 篇 冶金工程
- 5 篇 光学工程
- 3 篇 核科学与技术
- 3 篇 农业工程
201 篇 理学
- 165 篇 数学
- 37 篇 物理学
- 19 篇 统计学（可授理学、...
- 17 篇 生物学
- 8 篇 化学
- 8 篇 系统科学
55 篇 管理学
- 47 篇 管理科学与工程(可...
- 30 篇 工商管理
- 9 篇 图书情报与档案管...
14 篇 经济学
- 14 篇 应用经济学
10 篇 法学
- 8 篇 社会学
3 篇 农学
3 篇 医学
2 篇 教育学

主题

426 篇 field programmab...
220 篇 field programmab...
72 篇 hardware
40 篇 computer archite...
29 篇 clocks
27 篇 software
27 篇 fpga
24 篇 routing
21 篇 table lookup
19 篇 acceleration
18 篇 random access me...
17 篇 computational mo...
17 篇 real-time system...
16 篇 logic gates
14 篇 registers
13 篇 delays
13 篇 throughput
13 篇 switches
13 篇 kernel
13 篇 digital signal p...

机构

7 篇 univ of toronto ...
6 篇 school of comput...
6 篇 univ of toronto
5 篇 university of to...
5 篇 univ of californ...
5 篇 altera corporati...
5 篇 intel corporatio...
4 篇 univ british col...
4 篇 department of el...
4 篇 dept. of cs 256-...
4 篇 department of el...
3 篇 computer science...
3 篇 tsinghua univers...
3 篇 department of ee...
3 篇 xilinx inc. san ...
3 篇 politecn milan d...
3 篇 fudan univ state...
3 篇 northwestern uni...
3 篇 state key lab of...
3 篇 nanyang technolo...

作者

22 篇 rose jonathan
19 篇 cong jason
12 篇 betz vaughn
10 篇 wawrzynek john
10 篇 chen deming
9 篇 dehon andré
9 篇 hauck scott
9 篇 zhang zhiru
8 篇 chow paul
7 篇 wilton steven j....
7 篇 schmit herman
7 篇 constantinides g...
7 篇 langhammer marti...
6 篇 cheung peter y. ...
6 篇 wilton steven j....
6 篇 pasca bogdan
6 篇 santambrogio mar...
6 篇 li fei
6 篇 prasanna viktor ...
6 篇 he lei

语言

795 篇 英文
6 篇 其他

检索条件"任意字段=2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA 2016"

共 801 条记录，以下是151-160 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

Heterogeneous technology mapping for fpgas with dual-port embedded memory arrays 00

Heterogeneous technology mapping for FPGAs with dual-port em...

引用

fpga 2000: acm/sigda international symposium on field programmable gate arrays

作者： Wilton, Steven J.E. Univ of British Columbia Vancouver BC Canada

ISBN: (纸本)9781581131932

It has become clear that on-chip storage is an essential component of high-density fpgas. These arrays were originally intended to implement storage, but recent work has shown that they can also be used to implement logic very efficiently. This previous work has only considered single-port arrays. Many current fpgas, however, contain dual-port arrays. In this paper we present an algorithm that maps logic to these dual-port arrays. Our algorithm can either optimize area with no regard for circuit speed, or optimize area under the constraint that the combinational depth of the circuit does not increase. Experimental results show that, on average, our algorithm packs between 29% and 35% more logic than an algorithm that targets single-port arrays. We also show, however, that even with this algorithm, dual-port arrays are still not as area-efficient as single-port arrays when implementing logic.

关键词： field programmable gate arrays

来源：评论

学校读者我要写书评

暂无评论

Impact of fpga architecture on resource sharing in high-level synthesis 12

Impact of FPGA architecture on resource sharing in high-leve...

引用

2012 acm/sigda international symposium on field programmable gate arrays, fpga'12

作者： Hadjis, Stefan Canis, Andrew Anderson, Jason H. Choi, Jongsok Nam, Kevin Brown, Stephen Czajkowski, Tomasz ECE Department University of Toronto Toronto ON Canada Altera Toronto Technology Centre Toronto ON Canada

ISBN: (纸本)9781450311557

Resource sharing is a key area-reduction approach in high-level synthesis (HLS) in which a single hardware functional unit is used to implement multiple operations in the high-level circuit specification. We show that the utility of sharing depends on the underlying fpga logic element architecture and that different sharing trade-offs exist when 4-LUTs vs. 6-LUTs are used. We further show that certain multi-operator patterns occur multiple times in programs, creating additional opportunities for sharing larger composite functional units comprised of patterns of interconnected operators. A sharing cost/benefit analysis is used to inform decisions made in the binding phase of an HLS tool, whose RTL output is targeted to Altera commercial fpga families: Stratix IV (dual-output 6-LUTs) and Cyclone II (4-LUTs). © 2012 acm.

关键词： field programmable gate arrays (fpga)

来源：评论

学校读者我要写书评

暂无评论

A memory coherence technique for online transient error recovery of fpga configurations 01

A memory coherence technique for online transient error reco...

引用

2001 acm/sigda 9th international Sysmposium on field programmable gate arrays (fpga 2001)

作者： Huang, W.-J. McCluskey, E.J. Center for Reliable Computing Department of Electrical Engineering Stanford University Stanford CA 94305-4055 United States

ISBN: (纸本)9781581133417

The partial reconfiguration feature of some of the current-generation field programmable gate arrays (fpgas) can improve dependability by detecting and correcting errors in on-chip configuration data. Such an error recovery process can be executed online with minimal interference of user applications. However, because Look-up Tables (LUTs) in Configurable Logic Blocks (CLBs) of fpgas can also implement memory modules for user applications, a memory coherence issue arises such that memory contents in user applications may be altered by the online configuration data recovery process. In this paper, we investigate this memory coherence problem and propose a memory coherence technique that does not impose extra constraints on the placement of memory-configured LUTs. Theoretical analyses and simulation results show that the proposed technique guarantees the memory coherence with a very small (on the order of 0.1%) execution time overhead in user applications.

关键词： field programmable gate arrays

来源：评论

学校读者我要写书评

暂无评论

Configuration prefetch for single context reconfigurable coprocessors 98

Configuration prefetch for single context reconfigurable cop...

引用

Proceedings of the 1998 acm/sigda 6th international symposium on field programmable gate arrays, fpga

作者： Hauck, Scott Northwestern Univ Evanston IL United States

ISBN: (纸本)9780897919784

Current reconfigurable systems suffer from a significant overhead due to the time it takes to reconfigure their hardware. In order to deal with this overhead, and increase the power of reconfigurable systems, it is important to develop hardware and software systems to reduce or eliminate this delay. In this paper we propose one technique for significantly reducing the reconfiguration latency: the prefetching of configurations. By loading a configuration into the reconfigurable logic in advance of when it is needed, we can overlap the reconfiguration with useful computation. We demonstrate the power of this technique, and propose an algorithm for automatically adding prefetch operations into reconfigurable applications. This results in a significant decrease in the reconfiguration overhead for these applications.

关键词： field programmable gate arrays

来源：评论

学校读者我要写书评

暂无评论

fpga switch block layout and evaluation 02

FPGA switch block layout and evaluation

引用

fpga 2002: Tenth acm international symposium on field-programmable gate arrays

作者： Schmit, Herman Chandra, Vikas Department of ECE Carnegie Mellon University Pittsburgh PA 15213 United States

ISBN: (纸本)9781581134520

This paper presents abstract layout techniques for a variety of fpga switch block architectures. We evaluate the relative density of subset, universal, and Wilton switch block architectures. For subset switch blocks of small size, we find the optimal implementations using a simple metric. We also develop a tractable heuristic that returns the optimal results for small switch blocks, and good results for large switch blocks. For switch blocks with general connectivity, we develop a representation and a layout evaluation technique. We use these techniques to compare a variety of small switch blocks. We find that the traditional Xilinx-style, subset switch block is superior to the other proposed architectures. Finally, we have hand-designed some small switch blocks to confirm our results.

关键词： field programmable gate arrays

来源：评论

学校读者我要写书评

暂无评论

Flexible multi-mode embedded floating-point unit for field programmable gate arrays

Flexible multi-mode embedded floating-point unit for field p...

引用

7th acm sigda international symposium on field-programmable gate arrays, fpga'09

作者： Chong, Yee Jern Parameswaran, Sri School of Computer Science and Engineering University of New South Wales Sydney Australia

ISBN: (纸本)9781605584102

Performance of field programmable gate arrays (fpgas) used for floating-point applications is poor due to the complexity of floating-point arithmetic. Implementing floatingpoint units on fpgas consume a large amount of resources. This makes fpgas less attractive for use in floating-point intensive applications. Therefore, there is a need for embedded floating-point units (FPUs) in fpgas. However, if unutilized, embedded FPUs waste space on the fpga die. To overcome this issue, we propose a flexible multi-mode embedded FPU for fpgas that can be configured to perform a wide range of operations. The floating-point adder and multiplier in our embedded FPU can each be configured to perform one double-precision operation or two single-precision operations in parallel. To increase flexibility further, access to the large integer multiplier, adder and shifters in the FPU is provided. Benchmark circuits were implemented on both a standard Xilinx Virtex-II fpga and on our fpga with embedded FPU blocks. The results using our embedded FPUs showed a mean area improvement of 5.2 times and a mean delay improvement of 5.8 times for the doubleprecision benchmarks, and a mean area improvement of 4.4 times and a mean delay improvement of 4.2 times for the single-precision benchmarks. Copyright 2009 acm.

关键词： Adders

来源：评论

学校读者我要写书评

暂无评论

Dual-Vt fpga design for leakage power reduction

Dual-Vt FPGA design for leakage power reduction

引用

acm/sigda Thirteenth acm international symposium on field programmable gate arrays - fpga 2005

作者： Kumar, Akhilesh Anis, Mohab Electrical and Computer Engineering University of Waterloo Waterloo Ont. N2L 3G1

Leakage power has been overshadowed by dynamic power minimization techniques in fpgas, and is a growing concern in programmable logic. This paper proposes a dual threshold voltage implementation of the fpga architecture for leakage power reduction. A CAD flow is developed for assigning high threshold voltage to the logic elements within the logic blocks of the fpga for leakage power reduction. The CAD flow ensures that all the logic blocks remain identical with respect to the number of high and low threshold voltage logic elements that each logic block contains. This CAD flow leads to a dual threshold voltage implementation for the fpga architecture. Results indicate that over 95% of the logic elements in the fpga can be assigned high threshold voltage. On an average leakage savings of 60% and up to 70% for some benchmarks can be achieved. The proposed CAD flow forms a basis on which other dual threshold voltage implementations of fpga can be evaluated. We investigate the design trade-offs between the ratio of the number of high and number of low-Vt logic elements in a cluster and the leakage savings. We also investigate the impact of cluster size on leakage savings for the dual threshold voltage implementation.

关键词： field programmable gate arrays

来源：评论

学校读者我要写书评

暂无评论

Using logic duplication to improve performance in fpgas

Using logic duplication to improve performance in FPGAs

引用

acm/sigda 11th acm international symposium on field programmable gate arrays

作者： Schabas, Karl Brown, Stephen D. Dept. of Elec. and Comp. Eng. University of Toronto Toronto Ont. Canada

The purpose of this paper is to introduce a modified packing and placement algorithm for fpgas that utilizes logic duplication to improve performance. The modified packing algorithm was designed to leave unused basic logic elements (BLEs) in timing critical clusters, to allow potential targets for logic duplication. The modified placement algorithm consists of a new stage after placement in which logic duplication is performed to shorten the length of the critical path. In this paper, we show that in a representative fpga architecture using .18 μm technology, the length of the final critical path can be reduced by an average of 14.1%. Approximately half of this gain comes directly from the changes to the packing algorithm while the other half comes from the logic duplication performed during placement.

关键词： field programmable gate arrays

来源：评论

学校读者我要写书评

暂无评论

Active leakage power optimization for fpgas

Active leakage power optimization for FPGAs

引用

acm/sigda Twelfth acm international symposium on field-programmable gate arrays - fpga 2004

作者： Anderson, Jason H. Najm, Farid N. Tuan, Tim ECE Department University of Toronto Toronto Ont. Canada Xilinx Toronto Development Centre Toronto Ont. Canada Xilinx Research Labs San Jose CA United States

We consider active leakage power dissipation in fpgas and present a "no cost" approach for active leakage reduction. It is well-known that the leakage power consumed by a digital CMOS circuit depends strongly on the state of its inputs. Our leakage reduction technique leverages a fundamental property of basic fpga logic elements (look-up-tables) that allows a logic signal in an fpga design to be interchanged with its complemented form without any area or delay penalty. We apply this property to select polarities for logic signals so that fpga hardware structures spend the majority of time in low leakage states. In an experimental study, we optimize active leakage power in circuits mapped into a state-of-the-art 90nm commercial fpga. Results show that the proposed approach reduces active leak-age by 25%, on average.

关键词： field programmable gate arrays

来源：评论

学校读者我要写书评

暂无评论

Novel high throughput reconfigurable fpga architecture

Novel high throughput reconfigurable FPGA architecture

引用

fpga 2000: acm/sigda international symposium on field programmable gate arrays

作者： Singh, Amit Macchiarulo, Luca Mukherjee, Arindam Marek-Sadowska, Malgorzata Univ of California Santa Barbara Santa Barbara United States

With increased logic density due to the shift towards Deep Submicron technologies (DSM), fpgas have become a viable option for implementing large designs. However, most commercial fpgas, due to their general purpose architectural nature, cannot handle designs which require very high throughput. In this paper, we propose a novel high throughput fpga architecture which tries to combine the high-performance of Application Specific Integrated Circuits (ASICs) and the flexibility afforded by the reconfigurability of fpgas. This architecture utilizes the concept of `Wave-Steering' and works best for designs which are highly regular and have almost equal delays along all paths. It has enormous potential in Digital Signal and Image Processing applications since a good portion of these applications are regular in nature. Preliminary results for some commonly used DSP designs are encouraging and yield throughputs in the neighborhood of 770 MHz in 0.5 μ CMOS technology.

关键词： field programmable gate arrays

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共81页 << < 12 13 14 15 16 17 18 19 20 21 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：