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Architecture evaluation for power-efficient fpgas

Architecture evaluation for power-efficient FPGAs

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acm/sigda 11th acm international symposium on field programmable gate arrays

作者： Li, Fei Chen, Deming He, Lei Cong, Jason Electrical Engineering Department University of California Los Angeles CA 90095 United States Computer Science Department University of California Los Angeles CA 90095 United States

This paper presents a flexible fpga architecture evaluation framework, named fpgaEVA-LP, for power efficiency analysis of LUT-based fpga architectures. Our work has several contributions: (i) We develop a mixed-level fpga power model that combines switch-level models for interconnects and macromodels for LUTs;(ii) We develop a tool that automatically generates a back-annotated gate-level netlist with post-layout extracted capacitances and delays;(iii) We develop a cycle-accurate power simulator based on our power model. It carries out gate-level simulation under real delay model and is able to capture glitch power;(iv) Using the frame work fpgaEVA-LP, we study the power efficiency of fpgas, in 0.10um technology, under various settings of architecture parameters such as LUT sizes, cluster sizes and wire segmentation schemes and reach several important conclusions. We also present the detailed power consumption distribution among different fpga components and shed light on the potential opportunities of power optimization for future fpga designs (e.g., ≤ 0.10um technology).

关键词： field programmable gate arrays

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An integrated framework for the high level design of high performance signal processing circuits on fpgas

An integrated framework for the high level design of high pe...

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acm/sigda Thirteenth acm international symposium on field programmable gate arrays - fpga 2005

作者： Benkrid, K. Belkacemi, S. School of Computer Science Queen's University of Belfast Belfast BT7 1NN United Kingdom

This paper proposes an integrated framework for the high level design of high performance signal processing algorithms' implementations on fpgas. The framework emerged from a constant need to rapidly implement increasingly complicated algorithms on fpgas while maintaining the high performance needed in many real time digital signal processing applications. This is particularly important for application developers who often rely on iterative and interactive development methodologies. The central idea behind the proposed framework is to dynamically integrate high performance structural hardware description languages with higher level hardware languages in other to help satisfy the dual requirement of high level design and high performance implementation. The paper illustrates this by integrating two environments: Celoxica's Handel-C language, and HIDE, a structural hardware environment developed at the Queen's University of Belfast.

关键词： field programmable gate arrays

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Efficient packet classification for network intrusion detection using fpga 05

Efficient packet classification for network intrusion detect...

引用

acm/sigda Thirteenth acm international symposium on field programmable gate arrays - fpga 2005

作者： Song, Haoyu Lockwood, John W. Department of CSE Washington University St. Louis United States

ISBN: (纸本)9781595930293

fpga technology has become widely used for real-time network intrusion detection. In this paper, a novel packet classification architecture called BV-TCAM is presented, which is implemented for an fpga-based Network Intrusion Detection System (NIDS). The classifier can report multiple matches at gigabit per second network link rates. The BV-TCAM architecture combines the Ternary Content Addressable Memory (TCAM) and the Bit Vector (BV) algorithm to effectively compress the data representations and boost throughput. A tree-bitmap implementation of the BV algorithm is used for source and destination port lookup while a TCAM performs the lookup of the other header fields, which can be represented as a prefix or exact value. The architecture eliminates the requirement for prefix expansion of port ranges. With the aid of a small embedded TCAM, packet classification can be implemented in a relatively small part of the available logic of an fpga. The design is prototyped and evaluated in a Xilinx fpga XCV2000E on the FPX platform. Even with the most difficult set of rules and packet inputs, the circuit is fast enough to sustain OC48 traffic throughput. Using larger and faster fpgas, the system can work at speeds greater than OC192. Copyright 2005 acm.

关键词： field programmable gate arrays

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A petri-net based pre-runtime scheduler for dynamically self-reconfiguration of fpgas

A petri-net based pre-runtime scheduler for dynamically self...

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acm/sigda Thirteenth acm international symposium on field programmable gate arrays - fpga 2005

作者： Eskinazi, Remy De Lima, Manoel E. Maciel, Paulo R. M. Valderrama, Carlos A. Filho, Abel G. Nascimento, Paulo S. B. Polytechnic School University of the State of Pernambuco Informatics Center Computer Engineering Group Federal University of Pernambuco

Dynamically Reconfigurable Systems (DRS) offer a very interesting alternative for embedded digital systems design. Tasks scheduling within a reconfigurable environment allows the development of systems with better execution performance, chip area economy and lower power consumption. This paper describes a Petri Net based methodology for the design of dynamically reconfigurable systems, where tasks scheduling has as prime objective the best temporal performance of the overall application. The methodology includes the generation of an embedded controller supporting the scheduling process in the target architecture.

关键词： field programmable gate arrays

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A 475 MHz Manycore fpga Accelerator for RTL Simulation 24

A 475 MHz Manycore FPGA Accelerator for RTL Simulation

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32nd acm international symposium on field-programmable gate arrays, fpga 2024

作者： Kashani, Sahand Emami, Mahyar Kamahori, Keisuke Pourghannad, Sepehr Raj, Ritik Larus, James R. Epfl Lausanne Switzerland University of Washington Seattle United States Georgia Tech Atlanta United States

ISBN: (纸本)9798400704185

This paper presents the implementation of Manticore: a manycore accelerator for parallel RTL simulation. Manticore packs up to 225 custom soft processors running at 475 MHz on a large fpga. Implementing manycore accelerators on fpgas is challenging as designers must reconcile the conflicting goals of maximizing the number of cores on the chip and clocking them at the highest possible frequency. Designers face two classes of constraints: (1) architectural constraints imposed by a large fpga's multi-die structure, and (2) physical constraints imposed by the fpga shell's size and placement. Physical design therefore plays a critical role in the implementation of manycore accelerators. We present physical design challenges faced during Manticore's implementation on the AMD Alveo U200 card - -a large fpga with a poorly-placed, wide shell that challenges physical implementation. © 2024 Owner/Author.

关键词： field programmable gate arrays (fpga)

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Accelerating ncRNA homology search with fpgas 13

Accelerating ncRNA homology search with FPGAs

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2013 acm/sigda international symposium on field programmable gate arrays, fpga 2013

作者： McVicar, Nathaniel Ruzzo, Walter L. Hauck, Scott Department of Electrical Engineering University of Washington Seattle WA 98195 United States Department of Computer Science and Engineering Department of Genome Sciences Fred Hutchinson Cancer Research Center Seattle WA 98109 United States

ISBN: (纸本)9781450318877

Over the last decade, the number of known biologically important non-coding RNAs (ncRNAs) has increased by orders of magnitude. The function performed by a specific ncRNA is partially determined by its structure, defined by which nucleotides of the molecule form pairs. These correlations may span large and variable distances in the linear RNA molecule. Because of these characteristics, algorithms that search for ncRNAs belonging to known families are computationally expensive, often taking many CPU weeks to run. To improve the speed of this search, multiple search algorithms arranged into a series of progressively more stringent filters can be used. In this paper, we present an fpga based implementation of some of these algorithms. This is the first fpga based approach to attempt to accelerate multiple filters used in ncRNA search. The fpga is reconfigured for each filter, resulting in a total system speedup of 25x when compared with a single CPU. © 2013 acm.

关键词： field programmable gate arrays (fpga)

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Stochastic, spatial routing for hypergraphs, trees, and meshes

Stochastic, spatial routing for hypergraphs, trees, and mesh...

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acm/sigda 11th acm international symposium on field programmable gate arrays

作者： Huang, Randy Wawrzynek, John DeHon, André UC Berkeley Soda Hall 1776 Berkeley CA 94720 United States Dept. of CS 256-80 California Institute Technology Pasadena CA 91125 United States

fpga place and route is time consuming, often serving as the major obstacle inhibiting a fast edit-compile-test loop in prototyping and development and the major obstacle preventing late-bound hardware and design mapping for reconfigurable systems. Previous work showed that hardware-assisted routing can accelerate fanout-free routing on Fat-Trees by three orders of magnitude with modest modifications to the network itself. In this paper, we show how these techniques can be applied to any fpga and how they can be implemented on top of LUT networks in cases where modification of the fpga itself is not justified. We further show how to accommodate fanout and how to achieve comparable route quality to software-based methods. For a tree network, we estimate an fpga implementation of our routing logic could route the Toronto Place and Route Benchmarks at least two orders of magnitude faster than a software Pathfinder while achieving within 3% of the aggregate quality. Preliminary results on small mesh benchmarks achieve within one track of vpr -fast.

关键词： field programmable gate arrays

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Circuit partitioning with complex resource constraints in fpgas 98

Circuit partitioning with complex resource constraints in FP...

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Proceedings of the 1998 acm/sigda 6th international symposium on field programmable gate arrays, fpga

作者： Liu, Huiqun Zhu, Kai Wong, D.F. Univ of Texas at Austin Austin TX United States

ISBN: (纸本)9780897919784

In this paper, we present an algorithm for circuit partitioning with complex resource constraints in large fpgas. Traditional partitioning methods estimate the capacity of an fpga device by counting the number of logic blocks, however this is not accurate with the increasing capacity and diverse resource types in the new fpga architectures. We propose a network flow based method to optimally check whether a circuit or a sub-circuit is feasible for a set of available heterogeneous resources. The feasibility checking procedure is integrated in the FM-based algorithm for circuit partitioning. Incremental flow technique is employed for efficient implementation. Experimental results on the MCNC benchmark circuits show that our partitioning algorithm not only yields good results, but also is efficient. Our algorithm for partitioning with complex resource constraints is applicable for both multiple fpga designs (e.g. logic emulation systems) and partitioning-based placement algorithms for a single large hierarchical fpga (e.g. Actel's ES6500 fpga family).

关键词： field programmable gate arrays

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Automatic generation of fpga routing architectures from high-level descriptions 00

Automatic generation of FPGA routing architectures from high...

引用

fpga 2000: acm/sigda international symposium on field programmable gate arrays

作者： Betz, Vaughn Rose, Jonathan Right Track CAD Corp Toronto Ont Canada

ISBN: (纸本)9781581131932

In this paper we present a `high-level' fpga architecture description language which lets fpga architects succinctly and quickly describe an fpga routing architecture. We then present an `architecture generator' built into the VPR CAD tool that converts this high-level architecture description into a detailed and completely specified flat fpga architecture. This flat architecture is the representation with which CAD optimization and visualization modules typically work. By allowing fpga researchers to specify an architecture at a high-level, an architecture generator enables quick and easy `what-if' experimentation with a wide range of fpga architectures. The net effect is a more fully optimized final fpga architecture. In contrast, when fpga architects are forced to use more traditional methods of describing an fpga (such as the manual specification of every switch in the basic tile of the fpga), far less experimentation can be performed in the same time, and the architectures experimented upon are likely to be highly similar, leaving important parts of the design space completely unexplored. This paper describes the automated routing architecture generation problem, and highlights the two key difficulties - creating an fpga architecture that matches all of an fpga architect's specifications, while simultaneously determining good values for the many unspecified portions of an fpga so that a high quality fpga results. We describe the method by which we generate fpga routing architectures automatically, and present several examples.

关键词： field programmable gate arrays

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Armada: Timing-driven pipeline-aware routing for fpgas

Armada: Timing-driven pipeline-aware routing for FPGAs

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14th acm/sigda international symposium on field programmable gate arrays - fpga 2006

作者： Eguro, Ken Hauck, Scott Electrical Engineering Department University of Washington Seattle WA

ISBN: (纸本)1595932925

While previous research has shown that fpgas can efficiently inclement many types of computations, their flexibility inherently limits their clock rate. Several research groups have attempted to address this by developing new architectures that include registered switchpoints within their interconnect. Unfortunately, this pipelined communication presents a new and difficult problem for detailed routing tools. Known as the N-Delay Routing Problem, it has been proven to be NP-Complete. Although there have been two heuristics developed to address this issue, both have certain limitations and neither approach considers timing during the routing process. While timing-driven conventional routing is largely considered to be a solved problem, there are several issues inherent to the N-Delay Routing problem make addressing timing particularly difficult, m this paper we discuss the nature of these problems and present a new timing-driven pipeline-aware router that produces as much as 60% better critical path delay than previous efforts. Copyright 2006 acm.

关键词： field programmable gate arrays

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