This article presents the performance evaluation of two new diagonal routing tracks in fpgas. We discuss the automatic detailed architecture generation issues and propose changes in the conventional placement and rout...
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ISBN:
(纸本)9781605584102
This article presents the performance evaluation of two new diagonal routing tracks in fpgas. We discuss the automatic detailed architecture generation issues and propose changes in the conventional placement and routing to suit these architectures better. We conduct a series of experiments on these architecture with MCNC Benchmarks, where key parameters are varied over practical ranges and we conclude that the results are well in accordance, as predicted by the theory. Copyright 2009 acm.
The size of configuration bitstreams of field-programmablegatearrays (fpga) is increasing rapidly. Compression techniques are used to decrease the size of bitstreams. In this paper, an appropriate bitstream format a...
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This paper describes the architectural configuration of the Electrically programmable Analog Circuit (EPAC), an expert cell approach to meeting the market need for an analog counterpart to the digital fpga. It provide...
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This paper describes the architectural configuration of the Electrically programmable Analog Circuit (EPAC), an expert cell approach to meeting the market need for an analog counterpart to the digital fpga. It provides an overview of the technology and describes the internal operation of the first commercial EPAC devices.
Multi-point distributed random variables whose moments match those of a Gaussian random variable up to a certain order play an important role in Monte Carlo simulations of weak approximations of stochastic differentia...
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Multi-point distributed random variables whose moments match those of a Gaussian random variable up to a certain order play an important role in Monte Carlo simulations of weak approximations of stochastic differential equations. In applications such as finance, where "real time" execution is required, there is a strong need for highly efficient implementations. In this paper a fast and flexible dedicated hardware solution on a fieldprogrammablegate Array (fpga) is presented. A comparative performance analysis between a software-only and the proposed hardware solution demonstrates that the fpga solution is bottleneck-free, retains the flexibility of the software solution and significantly increases the computational efficiency.
This paper presents a review of some existing architectures for the implementation of Montgomery modular multiplication and exponentiation on fpga (fieldprogrammablegate Array). Some new architectures are presented,...
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ISBN:
(纸本)9781581134520
This paper presents a review of some existing architectures for the implementation of Montgomery modular multiplication and exponentiation on fpga (fieldprogrammablegate Array). Some new architectures are presented, including a pipelined architecture exploiting the maximum carry chain length of the fpga which is used to implement the modular exponentiation operation required for RSA encryption and decryption. Speed and area comparisons are performed on the optimised designs. The issues of targeting a design specifically for a reconfigurable device are considered, taking into account the underlying architecture imposed by the target technology.
Multi-fieldprogrammablegate array (fpga) systems (MFS) are used as custom computing machines, logic emulators and rapid prototyping vehicles. A key aspect of these systems is their programmable routing architecture;...
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Multi-fieldprogrammablegate array (fpga) systems (MFS) are used as custom computing machines, logic emulators and rapid prototyping vehicles. A key aspect of these systems is their programmable routing architecture;the manner in which wires, fpgas and fieldprogrammable interconnect devices (FPID) are connected. A new routing architecture, called hybrid complete-graph and partial-crossbar (HCGP), which has superior speed and cost compared to a partial crossbar is proposed. The architecture uses both hard-wired and programmable connections between the fpgas.
In this paper, we present and analyze a sophisticated communication architecture that allows to integrate many different modules into a system by fpga reconfiguration at runtime. Furthermore, we examine how this archi...
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ISBN:
(纸本)9781605584102
In this paper, we present and analyze a sophisticated communication architecture that allows to integrate many different modules into a system by fpga reconfiguration at runtime. Furthermore, we examine how this architecture can be implemented on low-cost Spartan-3 devices. It will be demonstrated that modules can be exchanged in a system without disturbing the communication architecture. The paper points out, that the capabilities of Spartan-3 fpgas are sufficient to build complex reconfigurable systems. Copyright 2009 acm.
This paper describes an analytical model that relates the architectural parameters of an fpga to the average prerouting wirelength of an fpga implementation. Both homogeneous and heterogeneous fpgas are considered. Fo...
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ISBN:
(纸本)9781605584102
This paper describes an analytical model that relates the architectural parameters of an fpga to the average prerouting wirelength of an fpga implementation. Both homogeneous and heterogeneous fpgas are considered. For homogeneous fpgas, the model relates the lookup-table size, the cluster size, and the number of inputs per cluster to the expected wirelength. For heterogeneous fpgas, the number and positioning of the embedded blocks, as well as the number of pins on each embedded block is considered. Two applications of the model to fpga architectural design are also presented. Copyright 2009 acm.
As device densities increase, testing cost is becoming a larger portion of the overall fpga manufacturing cost. We present an approach to speed up testing fpga interconnect by reconfiguring it during the test. Simple ...
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ISBN:
(纸本)9781581134520
As device densities increase, testing cost is becoming a larger portion of the overall fpga manufacturing cost. We present an approach to speed up testing fpga interconnect by reconfiguring it during the test. Simple additions are made to create feedback shift register structures, which considerably reduce the number of test configurations for the switching matrix interconnect. This new testing architecture reduces switching matrix test time by 66% and the diagnosis time by 72%. The additions are transparent to the users both in terms of speed and functionality.
Latency insensitive communication oers many potential benets for fpga designs, including easier timing closure by enabling automatic pipelining, and easier interfacing with embedded NoCs. However, it is important to u...
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ISBN:
(纸本)9781450326711
Latency insensitive communication oers many potential benets for fpga designs, including easier timing closure by enabling automatic pipelining, and easier interfacing with embedded NoCs. However, it is important to understand the costs and trade-os associated with any new design style. This paper presents optimized implementations of latency insensitive communication building blocks, quanties their overheads in terms of area and frequency, and provides guidance to designers on how to generate high-speed and areae cient latency insensitive systems.
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