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检索条件"任意字段=2016 Conference on Design and Architectures for Signal and Image Processing, DASIP 2016"

共 951 条记录，以下是91-100 订阅

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Dataflow program analysis and refactoring techniques for design space exploration: MPEG-4 AVC/H.264 decoder implementation case study

Dataflow program analysis and refactoring techniques for des...

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2013 7th conference on design and architectures for signal and image processing, dasip 2013

作者： Ab Rahman, Ab Al-Hadi Casale Brunet, Simone Alberti, Claudio Mattavelli, Marco SCI-STI-MM École Polytechnique Fédérale de Lausanne Switzerland

ISBN: (纸本)9791092279016

This paper presents a methodology to perform design space exploration of complex signal processing systems implemented using the CAL dataflow language. In the course of space exploration, critical path in dataflow programs is first presented, and then analyzed using a new strategy for computational load reduction. These techniques, together with detecting design bottlenecks, point to the most efficient optimization directions in a complex network. Following these analysis, several new refactoring techniques are introduced and applied on the dataflow program in order to obtain feasible design points in the exploration space. For a MPEG-4 AVC/H.264 decoder software and hardware implementation, the multi-dimensional space can be explored effectively for throughput, resource, and frequency, with real-time decoding range from QCIF to HD resolutions.

关键词： Space research

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Hardware-software implementation of vehicle detection and counting using virtual detection lines 8

Hardware-software implementation of vehicle detection and co...

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8th conference on design and architectures for signal and image processing (dasip)

作者： Kryjak, Tomasz Komorkiewicz, Mateusz Gorgon, Marek AGH Univ Sci & Technol Fac Elect Engn Automat Comp Sci & Biomed Engn Dept Automat & Biomed Engn Al Mickiewicza 30 PL-30059 Krakow Poland

ISBN: (纸本)9791092279061

In this paper a hardware-software system for vehicle detection and counting at intersections is presented. It has been implemented and evaluated on the heterogeneous Zynq platform. The vehicle detection is based on the concept of virtual detection lines (VDL). Differences in colour, horizontal edges and Census transform results between areas around the VDL for two consecutive frames are used to disclosure particular vehicles. This part of the system is designed in hardware description language and implemented in the reconfigurable resources of the Zynq platform. Information about the vehicle presence, along with the time-spatial image obtained at the VDL are transmitted and processed on the ARM core integrated in the Zynq device. This allows to perform further analysis and eliminate false or multiple detections. The solution has been evaluated on several video sequences recorded in various conditions: sunny day (the occurrence of deep shadows), cloudy day, rain and night-time. The system could be an important element of an intelligent transportation system (ITS) i. e. applied in a smart camera.

关键词： Vehicle detection Smart cameras Intelligent transportation systems Video sequences Hardware design languages software implementation Virtual Intersection False

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Synthesis of arithmetic expressions for the fixed-point arithmetic: The Sardana approach

Synthesis of arithmetic expressions for the fixed-point arit...

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6th Annual conference on design and architectures for signal and image processing, dasip 2012

作者： Ioualalen, Arnault Martel, Matthieu Univ. Perpignan Via Domitia Digits Architectures et Logiciels Informatiques F-66860 Perpignan France Univ. Montpellier II Laboratoire d'Informatique Robotique et de Microelectronique de Montpellier UMR 5506 F-34095 Montpellier France CNRS Laboratoire d'Informatique Robotique et de Microelectronique de Montpellier UMR 5506 F-34095 Montpellier France

ISBN: (纸本)9782953998726

Sardana is a tool which optimizes the arithmetic expressions present in source codes. The optimization is done by synthesizing automatically new mathematically equal expressions, given ranges of values for the variables. In previous work, Sardana has been used to optimize the numerical accuracy of floating-point expressions, by minimizing the worst roundoff error on the result of the evaluation. In this article, we show how our tool can be used to synthesize arithmetic expressions optimized for the fixed-point arithmetic. In this context, Sardana minimizes the number of bits required to represent without overflow the integer parts of the fixed-point numbers possibly occurring at any stage of the evaluation of an expression. We present experimental results showing how our tool optimizes the implementation of digital filters commonly used in image processing. © 2012 ECSI.

关键词： Fixed point arithmetic

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Exploration platform of embedded SIMD architecture for autonomous retinas

Exploration platform of embedded SIMD architecture for auton...

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2010 conference on design and architectures for signal and image processing, dasip2010

作者： Chevobbe, Stéphane Pajaniradja, Suresh Letellier, Laurent CEA LIST Embedded Computing Laboratory Gif-sur-Yvette F-91191 France

ISBN: (纸本)9781424487356

An integrated smart camera is a single chip composed of a sensor tightly coupled with one or more processing elements. The image processing applications that are mapped on such systems can require processing power in the range of supercomputer. To face the increasing application needs we propose in this paper a SIMD based processor optimized for the low and intermediate level of image processing. The architecture is composed of several SIMD cluster. Each cluster includes a configurable number of 2-Way PE (processing Element) ranging from 32 to 256 running at 200 MHz. These cluster configurations provide between 12 to 102 GOPS. © 2010 IEEE.

关键词： image processing

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Exploring the Concurrent Execution of HEVC Intra Encoding Algorithms for Heterogeneous Multi Core architectures

Exploring the Concurrent Execution of HEVC Intra Encoding Al...

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conference on design and architectures for signal & image processing

作者： Brandenburg, Jens Stabernack, Benno Heinrich Hertz Inst Nachrichtentech Berlin GmbH Fraunhofer Inst Telecommun Video Coding & Analyt Dept Embedded Syst Grp Einsteinufer 37 D-10587 Berlin Germany

ISBN: (纸本)9791092279115

By introducing novel algorithms in the emerging high efficiency video coding (HEVC) standard average bit-rate savings of 23% have been achieved in comparison to the H.264/AVC high profile reference encoder for the all intra configuration at the cost of an additional complexity increase. This high algorithmic complexity requires the development and integration of innovative approaches, like different parallelization strategies, heterogeneous designs and/or algorithmic optimizations, resulting in a complex design space. Early design verifications as well as performance evaluations are crucial to realize successful solutions, which meet the functional and non-functional constrains respectively. In this paper we propose a SystemC based heterogeneous multi-core model of an HEVC intra encoder, which is used to explore different design aspects and alternatives. Due to its cycle accurate nature the model is well suited to facilitate various performance evaluations and to drive HW/SW co-optimizations of the explored system, as we will discuss in this paper.

关键词： Algorithm design and analysis Encoding Estimation Optimization Prediction algorithms Standards Transforms

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design and analysis of an FPGA based encoder SoC for locally stationary image source

Design and analysis of an FPGA based encoder SoC for locally...

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2013 7th conference on design and architectures for signal and image processing, dasip 2013

作者： Bai, Yuhui Ahmed, Syed-Zahid Granado, Bertrand ETIS - ENSEA - Université Cergy Pontoise - CNRS Cergy France LIP6 - Université Pierre et Marie Curie - CNRS Paris France

ISBN: (纸本)9791092279016

Hierarchical Enumerative Coding (HENUC) is a lossless compression algorithm used in a wavelet based image encoder. By manipulating the wavelet coefficients into locally stationary sequences, HENUC is demonstrated to provide good compression efficiency according to our experimental results. We extended our previous work on FPGA encoder SoC, exploiting an innovative on-chip memory access manner in the bit-plane coding using dual port, as well as an address-based data traversal technique during the coding. Performance results are based on the Altera's 40nm Stratix IV EP4SGX230 FPGA, on a DE4 board from Terasic, where the optimized dual port HENUC architecture is implemented in a Nios II processor based system on chip. We present the resource utilization and the execution time evaluations. We show that our implementation at 100MHz can provide around 10X speedup over 2.4GHz Intel Xeon 8-core CPU, which is about twice as faster as our previous result.

关键词： System-on-chip

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Exploring Custom Heterogeneous MPSoCs for Real-Time Neural signal Decoding

Exploring Custom Heterogeneous MPSoCs for Real-Time Neural S...

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conference on design and architectures for signal & image processing

作者： Meloni, Paolo Tuveri, Giuseppe Pani, Danilo Raffo, Luigi Palumbo, Francesca Univ Cagliari Dipartimento Ingn Elettr & Elettron I-09123 Cagliari Italy Univ Sassari PolComIng Grp Ingn Informaz I-07100 Sassari Italy

ISBN: (纸本)9791092279115

The design of embedded systems for neuroprosthetic applications represents an important challenge to be faced in electronic bioengineering. One of the key research problems is decoding the information encoded in neural signals to extract the patient's motion intention. How to implement a highly-portable and reliable integrated solution is still an open issue. In this paper, we investigate the possibility of adopting the MPSoC paradigm in this application domain, presenting a design space exploration that evaluates different custom MPSoC embedded architectures, implementing an on-line neural signal decoding algorithm. The evaluated design points feature different mappings of parallel software tasks onto customized ASIP processing cores. Experimental results, obtained by FPGA-based prototyping, assess the performance and hardware-related costs of the considered configurations. The clock frequency needed to respect real-time constraints was reduced to 22 MHz, making a step further towards the exploitation of custom heterogeneous MPSoCs for ultra-low power biomedical signal processing.

关键词： Algorithm design and analysis Computer architecture Decoding Noise reduction Program processors Real-Time systems Sorting

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Smart sensor architectures for embedded biosignal analysis

Smart sensor architectures for embedded biosignal analysis

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2013 7th conference on design and architectures for signal and image processing, dasip 2013

作者： Pfundt, Benjamin Reichenbach, Marc Eskofier, Björn Fey, Dietmar Department Computer Science Computer Architecture Friedrich-Alexander-University Erlangen-Nuremberg Germany Department Computer Science Pattern Recognition Lab Friedrich-Alexander-University Erlangen-Nuremberg Germany

ISBN: (纸本)9791092279016

In many sports and medical applications small and wearable sensors are used that capture motion and physiological signals. Yet, commonly such sensor are only capable of acquiring raw data, which is afterwards transmitted to a smartphone or other mobile computing device where processing and classification is carried out. This results in limited usability because another device has to be worn. Moreover, high power consumption due to continuous transmission is a main disadvantage. Therefore, we propose a smart sensor approach that can alleviate these problems by carrying out the processing on the sensor itself. To house the processing schemes in the sensor node we developed a new computer architecture utilizing an FPGA and an ASIC. To show the benefits of the in-sensor processing, we chose two representative biosensor applications: a movement and fall detection system for the elderly and a swimming style recognition system for professional athletes. Compared to conventional approaches the same classification rate can be achieved while saving space, power, weight and setup costs.

关键词： Field programmable gate arrays (FPGA)

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design under constraints of availability and energy for sensor node in wireless sensor network

Design under constraints of availability and energy for sens...

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6th Annual conference on design and architectures for signal and image processing, dasip 2012

作者： Hoang, Van-Trinh Julien, Nathalie Berruet, Pascal Lab-STICC/University of South-Brittany Research Center BP 92116 56321 Lorient France

ISBN: (纸本)9782953998726

Wireless Sensor Network (WSN) technology has been getting a lot of attention in recent years due to its low-cost, portability, easy deployment, self-organisation, and reconfigurability. Two main challenges faced by designers are availability and power/energy management for WSN. This paper presents a design for a wireless sensor node, which provides automated reconfiguration for both availability and energy-efficient use. This design introduces an original device named Power and Availability Manager (PAM) combined with a FPGA. The first one is considered as the intelligent part for the best use of energy and fault-tolerance, while the other enhances the availability in case of hardware failure for a node. Simulation model of these solutions together is based on General Stochastic Petri Net (GSPN). The results indicate a gain of availability from 9% to 31% for sensor node over twelve years, from 9% to 46% for sensor cluster over eighteen years, from 11% to 45% for whole network over fifty years. Our approach also results in significant energy-saving : up to 61% by using DPM policy, and up to 62.5% by using DPM and DVFS policies over seven days. These results allow us to evaluate and to show a design of WSN node for increased availability as well as energy-saving by using our approach. © 2012 ECSI.

关键词： Energy efficiency

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Fast and Efficient signals Recovery for Deterministic Compressive Sensing: Applications to Biosignals

Fast and Efficient Signals Recovery for Deterministic Compre...

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conference on design and architectures for signal & image processing

作者： Ravelomanantsoa, Andrianiaina Rabah, Hassan Rouane, Amar Univ Lorraine IJL UMR7198 F-54506 Vandoeuvre Les Nancy France

ISBN: (纸本)9791092279115

Compressed sensing is a technique that is suitable for compressing and recovering signals having sparse representations in certain bases. Compressed sensing has been widely used to optimize the measurement process of power and bandwidth constrained systems like wireless body sensor network. The central issues with compressed sensing are mainly the construction of measurement matrices and the development of efficient recovery algorithms. In this paper, we proposed a simple and fast recovery algorithm which performed a thresholding in the discrete cosine transform domain. We validated it by recovering electrocardiogram and electromyogram signals taken from the Phyiobank database. The simulation and experimental results have shown that the proposed recovery algorithm was 25 and 12 times faster than orthogonal matching pursuit and stagewise orthogonal matching pursuit, respectively. In addition, depending on the compression ratio, the signal-to-noise ratio of recovered signals were improved up to 2 dB.

关键词： Atmospheric measurements Discrete cosine transforms Matching pursuit algorithms Particle measurements signal processing algorithms Sparse matrices

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