The proceedings contain 13 papers. The special focus in this conference is on design and Architecture for signal and imageprocessing. The topics include: Exploring Fully Convolutional Networks for the Segme...
ISBN:
(纸本)9783031127472
The proceedings contain 13 papers. The special focus in this conference is on design and Architecture for signal and imageprocessing. The topics include: Exploring Fully Convolutional Networks for the Segmentation of Hyperspectral Imaging Applied to Advanced Driver Assistance Systems;an Adaptable Cognitive Microcontroller Node for Fitness Activity Recognition;towards Real-Time and Energy Efficient Siamese Tracking – A Hardware-Software Approach;Low Latency Architecture design for Decoding 5G NR Polar Codes;Efficient Software and Hardware Implementations of a QCSP Communication System;Dynamic Pruning for Parsimonious CNN Inference on Embedded Systems;DL-CapsNet: A Deep and Light Capsule Network;Comparative Study of Scheduling a Convolutional Neural Network on Multicore MCU;influence of Dataflow Graph Moldable Parameters on Optimization Criteria;QoS Aware design-Time/Run-Time Manager for FPGA-Based Embedded Systems;fixed-Point Code Synthesis Based on Constraint Generation.
The proceedings contain 10 papers. The special focus in this conference is on design and architectures for signal and imageprocessing. The topics include: LiFT: Lightweight, FPGA-Tailored 3D Object Detection Based on...
ISBN:
(纸本)9783031878961
The proceedings contain 10 papers. The special focus in this conference is on design and architectures for signal and imageprocessing. The topics include: LiFT: Lightweight, FPGA-Tailored 3D Object Detection Based on LiDAR Data;A Practical HW-Aware NAS Flow for AI Vision Applications on Embedded Heterogeneous SoCs;Endoscopy image Classification for Wireless Capsules with CNNs on Microcontroller-Based Platforms;joint Underwater Depth Estimation and Dehazing from a Single image Using Attention U-Net;KD-AHOSVD: Neural Network Compression via Knowledge Distillation and Tensor Decomposition;Novel Scheduling and Shifter Networks for 5G LDPC Decoders;Comparison Between In-Core Hardware IDS, Off-Core Hardware IDS and Software IDS;comparative Study of Memory Optimization Techniques for Dataflow-Modeled Applications.
We are pleased to welcome you to the beautiful island of Sardinia. dasip 2013 is the 7 th in a successful series. Past conferences took place in Karlsruhe, Tampere, Edinburgh, Nice, Brussels, and Grenoble. This new e...
We are pleased to welcome you to the beautiful island of Sardinia. dasip 2013 is the 7 th in a successful series. Past conferences took place in Karlsruhe, Tampere, Edinburgh, Nice, Brussels, and Grenoble. This new edition proposes a very attractive program with keynote speeches, contributed paper sessions, poster sessions, a demo night, and special sessions on timely topics.
This document describes a demonstration, proposed at dasip Demo Night session. This demonstration is running on a low-power manycore processor from Kalray, named MPPA (R) and is highlighting capabilities of this new g...
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ISBN:
(纸本)9791092279153
This document describes a demonstration, proposed at dasip Demo Night session. This demonstration is running on a low-power manycore processor from Kalray, named MPPA (R) and is highlighting capabilities of this new generation chip in processing multiple applications.
Overlays are reconfigurable architectures synthesized on commercial of the shelf (COTS) FPGAs. Overlays bring some advantages such as portability, resources abstraction, fast configuration, and can exhibit features in...
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ISBN:
(纸本)9791092279153
Overlays are reconfigurable architectures synthesized on commercial of the shelf (COTS) FPGAs. Overlays bring some advantages such as portability, resources abstraction, fast configuration, and can exhibit features independent from the host FPGA. We designed a fine-grained overlay implementing novel features easing the management of such architectures in a cluster of heterogeneous COTS FPGAs. This demonstration shows the use of this overlay in an FPGA cluster, performing a hardware application live migration between two nodes of a cluster. It also illustrates fault tolerance of the cluster.
In this paper a hardware-software implementation of adaptive correlation filter tracking for a 3840 x 2160 @ 60 fps video stream in a Zynq UltraScale+ MPSoC is discussed. Correlation filters gained popularity in recen...
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ISBN:
(纸本)9781728140742
In this paper a hardware-software implementation of adaptive correlation filter tracking for a 3840 x 2160 @ 60 fps video stream in a Zynq UltraScale+ MPSoC is discussed. Correlation filters gained popularity in recent years because of their efficiency and good results in the VOT (Visual Object Tracking) challenge. An implementation of the MOSSE (Minimum Output Sum of Squared Error) algorithm is presented. It utilizes 2-dimensional FFT for computing correlation and updates filter coefficients in every frame. The initial filter coefficients are computed on the ARM processor in the PS (processing System), while all other operations are preformed in PL (Programmable Logic). The presented architecture was described with the use of Verilog hardware description language.
In this paper hardware implementation of selected contextual based image pre-processing modules for a 3840x2160 @60 fps video stream in a Zynq UltraScale+ MPSoC is discussed. The following operations are considered: s...
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ISBN:
(纸本)9781538682371
In this paper hardware implementation of selected contextual based image pre-processing modules for a 3840x2160 @60 fps video stream in a Zynq UltraScale+ MPSoC is discussed. The following operations are considered: simple averaging (box filter), Gaussian filter, edge detection using the Sobel and Canny methods, median filter and morphological erosion and dilation operations. The scheme for implementing contextual based operations for a video stream in the format of 2 and 4 pixels per clock and challenges related to the pipelined implementation of processing such data are described. Also the use of logic resources and energy efficiency of modules described in the Verilog hardware description language and using the High Level Synthesis tools (Vivado HLS, SDSoC and xfOpenCV library) are compared. All designed modules support real-time processing of a 4K@60 fps video stream.
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