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检索条件"任意字段=2016 Conference on Design and Architectures for Signal and Image Processing, DASIP 2016"

共 951 条记录，以下是61-70 订阅

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Interfacing and scheduling legacy code within the canals framework

Interfacing and scheduling legacy code within the canals fra...

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2011 conference on design and architectures for signal and image processing, dasip 2011

作者： Dahlin, Andreas Jokhio, Fareed Lilius, Johan Gorin, Jérôme Raulet, Michaël Turku Centre for Computer Science Department of Information Technologies Åbo Akademi University Turku Finland IETR/Image Group Laboratory INSA Rennes Rennes France

ISBN: (纸本)9781457706196

The need for understanding how to distribute computations across multiple cores, have obviously increased in the multi-core era. Scheduling the functional blocks of an application for concurrent execution requires not only a good understanding of data dependencies, but also a structured way to describe the intended scheduling. In this paper we describe how the Canals language and its scheduling framework can be used for the purpose of scheduling and executing legacy code. Additionally a set of translation guidelines for translating RVC-CAL applications into Canals are presented. The proposed approaches are applied to an existing MPEG-4 Simple Profile decoder for evaluation purposes. The inverse discrete cosine transform (IDCT) is accelerated by the means of OpenCL. © 2011 IEEE.

关键词： Scheduling

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Acceleration of image reconstruction in 3D ultrasound computer tomography: An evaluation of CPU, GPU and FPGA computing

Acceleration of image reconstruction in 3D ultrasound comput...

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2011 conference on design and architectures for signal and image processing, dasip 2011

作者： Birk, Matthias Guth, Alexander Zapf, Michael Balzer, Matthias Ruiter, Nicole Hübner, Michael Becker, Jürgen Karlsruhe Germany

ISBN: (纸本)9781457706196

As today's standard screening methods frequently fail to diagnose breast cancer before metastases have developed, earlier breast cancer diagnosis is still a major challenge. Three-dimensional ultrasound computer tomography promises high-quality images of the breast, but is currently limited by a time-consuming synthetic aperture focusing technique based image reconstruction. In this work, we investigate the acceleration of the image reconstruction by a GPU, and by the FPGAs embedded in our custom data acquisition system. We compare the obtained performance results with a recent multi-core CPU and show that both platforms are able to accelerate processing. The GPU reaches the highest performance. Furthermore, we draw conclusions in terms of applicability of the accelerated reconstructions in future clinical application and highlight general principles for speed-up on GPUs and FPGAs. © 2011 IEEE.

关键词： Field programmable gate arrays (FPGA)

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Optimized fixed point implementation of a local stereo matching algorithm onto C66x DSP 8

Optimized fixed point implementation of a local stereo match...

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8th conference on design and architectures for signal and image processing (dasip)

作者： Menant, Judicael Pressigout, Muriel Morin, Luce Nezan, Jean-Francois Univ Europeenne Bretagne CNRS INSA IETRUMR 6164 20 Ave Buttes Coesmes F-35708 Rennes France

ISBN: (纸本)9791092279061

Stereo matching techniques aim at reconstructing disparity maps from a pair of images. The use of stereo matching techniques in embedded systems is very challenging due to the complexity of the state-of-the-art algorithms. An efficient local stereo matching algorithm has been chosen from the literature and implemented on a c6678 DSP. Arithmetic simplifications such as approximation by piecewise linear functions and fixed point conversions are proposed. Thanks to factorisation and precomputing, the memory footprint is reduced by a factor 13 to fit on the memory footprint available on embedded systems. A 14.5 fps speed (factor 60 speed-up) has been reached with a small quality loss on the final disparity map.

关键词： Fixed point Embedded systems Digital signal processing Desmoplakin Gene linear function mass loss N-ethylcarbaminomethyl-L-isoleucine Velocity coefficient factorization

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FPGA-based Real Time Embedded Hough Transform Architecture for circles detection 12

FPGA-based Real Time Embedded Hough Transform Architecture f...

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12th conference on design and architectures for signal and image processing (dasip)

作者： Chuquimia, Orlando Pinna, Andrea Marsala, Christophe Dray, Xavier Bertrand, Granado Sorbonne Univ CNRS LIP6 UMR 7606 Paris France Sorbonne Univ Hop St Antoine AP HP Paris France

ISBN: (纸本)9781538682371

Hough Transform is a widely used shapebased algorithm for object detection and localization [6], this technique can be generalized to parametric curves as circles. For a real time execution and embedded integration, several optimizations are necessary due to the large memory and computational requirements. This paper presents an efficient real-time pipelined architecture with a FPGA implementation of our Hough Transform for multi-circles detection. The computation of center candidates was improved. A three stages pipeline architecture was designed in order to reduce the processing latency and cadence. The architecture has been integrated into a Xilinx Zynq-7000 XC7Z020 containing a FPGA Artix-7. The global system uses 78.5 BRAMs, 153 DSP slices, 21638 LUTs. Our global system can support a maximum clock frequency of 128.89 MHz. We validate our architecture using a 125MHz clock frequency and we obtain a latency of 33.214 ms and an interval between two images of 16,607 ms for a 1920x1080 pixels image. According to our results, our architecture offer a throughput more than 4 times better than the faster state of the art architecture.

关键词： Transforms Histograms Computer architecture Field programmable gate arrays image edge detection Real-time systems Hardware

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design of a processor optimized for syntax parsing in video decoders

Design of a processor optimized for syntax parsing in video ...

引用

2011 conference on design and architectures for signal and image processing, dasip 2011

作者： Siret, Nicolas Nezan, Jean-François Rhatay, Aimad European University of Brittany INSA IETR F-35708 Rennes France Lead Tech. Design F-35700 Rennes France

ISBN: (纸本)9781457706196

Heterogeneous platforms aim to offer both performance and flexibility by providing designers processors and programmable logical units on a single platform. Processors implemented on these platforms are usually soft-cores (e.g. Altera NIOS) or ASIC (e.g. ARM Cortex-A8). However, these processors still face limitations in terms of performance compared to full hardware designs in particular for real-time video decoding applications. We present in this paper an innovative approach to improve performance using both a processor optimized for the syntax parsing (an Application-Specific Instruction-set Processor) and a FPGA. The case study has been synthesized on a Xilinx FPGA at a frequency of 100 MHz and we estimate the performance that could be obtained with an ASIC. © 2011 IEEE.

关键词： Field programmable gate arrays (FPGA)

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A New Real-Time Embedded Video Denoising Algorithm 13

A New Real-Time Embedded Video Denoising Algorithm

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conference on design and architectures for signal and image processing (dasip)

作者： Petreto, Andrea Romera, Thomas Lemaitre, Florian Masliah, Ian Gaillard, Boris Bouyer, Manuel Meunier, Quentin L. Lacassagne, Lionel Sorbonne Univ CNRS LIP6 F-75005 Paris France Lheritier Alcen F-95862 Cergy Pontoise France

ISBN: (纸本)9781728140742

Many embedded applications rely on video processing or on video visualization. Noisy video is thus a major issue for such applications. However, video denoising requires a lot of computational effort and most of the state-of-the-art algorithms cannot be run in real-time at camera framerate. This article introduces a new real-time video denoising algorithm for embedded platforms called RTE-VD. We first compare its denoising capabilities with other online and offline algorithms. We show that RTE-VD can achieve real-time performance (25 frames per second) for qHD video (960x540 pixels) on embedded CPUs and the output image quality is comparable to state-of-the-art algorithms. In order to reach real-time denoising, we applied several high-level transforms and optimizations (SIMDization, multi-core parallelization, operator fusion and pipelining). We study the relation between computation time and power consumption on several embedded CPUs and show that it is possible to determine different frequency and core configurations in order to minimize either the computation time or the energy.

关键词： Embedded system Video denoising Real-time image processing night-vision SIMD

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Energy Efficiency and Performance Management of Parallel Dataflow Applications 8

Energy Efficiency and Performance Management of Parallel Dat...

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8th conference on design and architectures for signal and image processing (dasip)

作者： Holmbacka, Simon Nogues, Erwan Pelcat, Maxime Lafond, Sebastien Lilius, Johan Abo Akad Univ Dept Informat Technol Turku Finland INSA Rennes CNRS UMR 6164 IETRImage Grp Rennes France

ISBN: (纸本)9791092279061

Parallelizing software is a popular way of achieving high energy efficiency since parallel applications can be mapped on many cores and the clock frequency can be lowered. Perfect parallelism is, however, not often reached and different program phases usually contain different levels of parallelism due to data dependencies. Applications have currently no means of expressing the level of parallelism, and the power management is mostly done based on only the workload. In this work, we provide means of expressing QoS and levels of parallelism in applications for more tight integration with the power management to obtain optimal energy efficiency in multi-core systems. We utilize the dataflow framework PREESM to create and analyze program structures and expose the parallelism in the program phases to the power management. We use the derived parameters in a NLP (Non Linear Programming) solver to determine the minimum power for allocating resources to the applications.

关键词： Power manager Multi-core Application Parallelism Dataflow framework

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Low Power image processing Applications on FPGAs Using Dynamic Voltage Scaling and Partial Reconfiguration 12

Low Power Image Processing Applications on FPGAs Using Dynam...

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12th conference on design and architectures for signal and image processing, dasip 2018

作者： Podlubne, Ariel Haase, Julian Kalms, Lester Akgün, Gökhan Ali, Muhammad Ul Hasan Khar, Habib Kamal, Ahmed Göhringer, Diana Technische Universität Dresden Germany

ISBN: (纸本)9781538682371

The TULIPP project aims to facilitate the development of embedded image processing systems with real-time and low-power constraints. In this paper, several adaptive dynamic runtime techniques for reconfigurable SoCs are described. These methods are used for low power image processing applications on high-performance embedded platforms. Dynamic voltage scaling and dynamic partial reconfiguration target the low-power requirements of the embedded systems while debugging supports the fast development on the hardware side of the system. The proposed techniques were tested and verified using an own developed custom SDSoC image processing library. © 2018 IEEE.

关键词： Embedded systems

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A unified hardware/software co-synthesis solution for signal processing systems

A unified hardware/software co-synthesis solution for signal...

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2011 conference on design and architectures for signal and image processing, dasip 2011

作者： Bezati, Endri Yviquel, Hervé Raulet, Michaël Mattavelli, Marco Ecole Polytechnique Fédérale de Lausanne CH-1015 Lausanne Switzerland IRISA University of Rennes 1 F-22300 Lannion France IETR INSA of Rennes F-35708 Rennes France

ISBN: (纸本)9781457706196

This paper presents a methodology to specify from a high-level data-flow description an application for both hardware and software synthesis. Firstly, an introduction to RVC-Cal data-flow programming and Orcc framework is presented. Furthermore, an analysis of a close to gate intermediate representation (XLIM) is bestowed. As a proof of concept a JPEG codec was written purely in RVC-Cal to test the co-synthesis tools and then an analysis of the generated hardware and software results are given. Our experience shows that using RVC-Cal can unify the process of creating the same application for software and hardware without modifying a single source code for each solution. © 2011 IEEE.

关键词： Field programmable gate arrays (FPGA)

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Consumption analysis and estimation in the design of GStreamer based multimedia applications

Consumption analysis and estimation in the design of GStream...

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6th Annual conference on design and architectures for signal and image processing, dasip 2012

作者： Lanoe, Mickael Senn, Eric Lab-STICC Université de Bretagne Sud France

ISBN: (纸本)9782953998726

Multimedia application development on embedded systems requires highly sophisticated hardware/software frameworks. These frameworks make heavy use of available hardware resources and therefore the impact on the overall consumption is far from negligible. Being able to determine this impact is therefore essential. In order to tackle this challenge, this paper proposes a methodology for modeling the power and energy consumption of multimedia applications, which allows a rapid performance analysis of combined signal and image processing on complex embedded systems. This methodology is applied to the GStreamer multimedia framework running on Linux operating system for the OMAP3530 heterogeneous MPSoC. Our approach is based on measurements of the power consumption during the rendering of compressed audio/video streams. Resulting power models consider features of the source stream such as the duration, video resolution, audio sampling frequency and bitrate. The precision of our models is presented and finally compared to the actual measurements for two full multimedia clips. © 2012 ECSI.

关键词： Embedded systems

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