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检索条件"任意字段=2016 Conference on Design and Architectures for Signal and Image Processing, DASIP 2016"

共 951 条记录，以下是701-710 订阅

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Flexible FPGA-Based architectures for Curve Point Multiplication over GF(p)

Flexible FPGA-Based Architectures for Curve Point Multiplica...

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Euromicro Symposium on Digital System design

作者： Dorian Amiet Andreas Curiger Paul Zbinden HSR Hochschule für Technik IMES Institut für Mikroelektronik und Embedded Systems Rapperswil Switzerland Securosys SA Zürich Switzerland

Elliptic curve cryptography (ECC) is widely used as an efficient mechanism to secure private data using public-key protocols. This paper focuses on ECC over prime fields (GF(p)). We present a novel hardware architecture that calculates the elliptic curve point multiplication (ECPM). Our processor supports arbitrary prime fields with sizes up to 1024 bits. Different standards, which use curves in short Weierstrass form are supported. A Xilinx Virtex-7 implementation of the proposed hardware architecture takes from 0.69 ms for a 192-bit point multiplication up to 9.7 ms for 512-bit. The implementation takes only 20 DSP slices and 6816 LUTs. To the authors knowledge, this is the best performance reported so far for ECC point multiplication for arbitrary prime field curves without the use of FPGA reconfiguration.

关键词： Computer architecture Elliptic curve cryptography Hardware Clocks Digital signal processing Elliptic curves Pipelines

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A compact multi-mode CORDIC with Global-Shifting-Sum (GSS) method

A compact multi-mode CORDIC with Global-Shifting-Sum (GSS) m...

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IEEE Asia-Pacific conference on Circuits and Systems

作者： Gihoon Jung Kyungrak Choi Jongsun Park Dept. of Electrical and Electronic Engineering Korea University Seoul South Korea

ISBN: (纸本)9781509015719

Coordinate Rotational Digital Computer (CORDIC) has been widely used as an iterative algorithm for performing rotations in many digital signal processing (DSP) applications. The CORDIC algorithm is divided into two modes, which are the rotation and vectoring modes. The conventional hardware architecture of CORDIC algorithm has two problems. First, though the computations of both modes are very similar, two separate modules are used in separate hardware architecture. Second, after computations of the whole iterations, an extra scaling operation to make a normalized output has been another computational burden. In this paper, we present a compact multi-mode CORDIC architecture, where both of the rotation and vectoring modes can be performed using a shared hardware architecture. In addition, Global-Shifting-Sum (GSS) approach which uses one adder and one barrel shifter is also proposed to efficiently eliminate the scaling operation of CORDIC. The proposed multi-mode GSS CORDIC is implemented as the iterative cross-folded architecture to minimize the area of CORDIC. The experimental results with 65nm CMOS process show 42% area reduction compared to the conventional two separate hardware architectures of CORDIC with minor degradation in accuracy.

关键词： Decision support systems signal processing algorithms Frequency synthesizers Memory management Generators Algorithm design and analysis

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OpenCL programmable exposed datapath high performance low-power image signal processor

OpenCL programmable exposed datapath high performance low-po...

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Norchip

作者： Joonas Multanen Heikki Kultala Matias Koskela Timo Viitanen Pekka Jääskelainen Jarmo Takala Aram Danielyan Cristóvão Cruz Tampere University of Technology Finland Noiseless Imaging Ltd Finland

Sophisticated computational imaging algorithms require both high performance and good energy-efficiency when executed on mobile devices. Recent trend has been to exploit the abundant data-level parallelism found in general purpose programmable GPUs. However, for low-power mobile use cases, generic GPUs consume excessive amounts of power. This paper proposes a programmable computational imaging processor with 16-bit half-precision SIMD floating point vector processing capabilities combined with power efficiency of an exposed datapath. In comparison to traditional VLIW architectures with similar computational resources, the exposed datapath reduces the register file traffic and complexity. These and the specific optimizations enabled by the explicit programming model enable extremely good power-performance. When synthesized on a 28nm ASIC technology, the accelerator consumes 71mW of power while running a state-of-the-art denoising algorithm, and occupies only 0.2mm 2 of chip area. For the algorithm, energy usage per frame is 7mJ, which is 10x less than the best found GPU-based implementation.

关键词： Radio frequency Registers VLIW Computer architecture signal processing algorithms Hardware Ports (Computers)

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Multilevel thresholding selection based on chaotic multi-verse optimization for image segmentation

Multilevel thresholding selection based on chaotic multi-ver...

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International Joint conference on Computer Science and Software Engineering (JCSSE)

作者： Tanachapong Wangchamhan Sirapat Chiewchanwattana Khamron Sunat Department of Computer Science Khon Kaen University Khon Kaen Thailand

ISBN: (纸本)9781509020348

Multilevel thresholding is the most important method for image processing. Conventional multilevel thresholding methods have proven to be efficient in bi-level thresholding; however, when extended to multilevel thresholding, they prove to be computationally more costly, as they comprehensively search the optimal thresholds for the objective function. This paper presents a chaotic multi-verse optimizer (CMVO) algorithm using Kapur's objective function in order to determine the optimal multilevel thresholds for image segmentation. The proposed CMVO algorithm was applied to various standard test images, and evaluated by peak signal-to-noise ratio (PSNR) and structural similarity index (SSIM). The CMVO algorithm efficiently and accurately searched multilevel thresholds and reduced the required computational times.

关键词： Algorithm design and analysis image segmentation Grippers Optimization Linear programming Nickel Software algorithms

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HDMI microscope camera based on Hi3518E chip

HDMI microscope camera based on Hi3518E chip

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IEEE International conference on Progress in Informatics and Computing (PIC)

作者： Hongyan Ding Feihong Yu College of Optical Science and Engineering Zhejiang University Hangzhou China

ISBN: (纸本)9781509034857

This paper presents a low-cost and portable microscope camera with high definition multimedia interface (HDMI) based on Hi3518E chip. Aiming at the high demand of the microscope camera for the color restoration, a fast white balance method based on R, G, B statistical information and color correction matrix is proposed in this paper. Result of experiment shows that the proposed algorithm gets good effect in more scenes than Hi3518E algorithm. In order to make up limitation for Gamma curve in image signal processing (ISP) of Hi3518E, a fast algorithm for generating Gamma table is introduced, which achieves wider adjustment range of Gamma curve than Hi3518E algorithm. This makes the camera can adapt to more HDMI display devices. With the built-in user-friendly software, the microscope camera can be controlled by a USB mouse to take pictures and videos, adjust parameters of ISP and do simple measurements. The designed camera can be used in industrial field testing, teaching research and other fields.

关键词： image color analysis Microscopy Cameras Algorithm design and analysis signal processing algorithms Videos Hardware

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Low Power signal processing via Approximate Multiplier for Error-Resilient Applications

Low Power Signal Processing via Approximate Multiplier for E...

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IEEE International conference on Industrial and Information Systems

作者： Bharat Garg G K Sharma ABV-Indian Institute of Information Technology and Management Gwalior India

The exponentially enlarging usability and mushrooming features in the portable hand-held devices such as cellphone appeal for the highly energy-efficient designs as the user cannot tolerate power famished devices rather can manage with tiny degraded quality. The multimedia applications such as image/video processing are compute-intensive and require efficient designs which can be achieved by approximate designs with the feeble accord in accuracy. As multiplication is the most frequently used and highly energy-consuming arithmetic operation, in this paper, a low power approximate multiplier architecture (AMA) is proposed that significantly improves the design metrics. We evaluate the proposed AMA with various quality metrics and design an AMA embedded Gaussian smoothing filter (GSF). The simulation results show that AMA reduces 81.5% power consumption over accurate and 19.17% energy over the well-known approximate multiplier architecture. Further, the AMA embedded GSF reduces 6.2% area and 7.53% power consumption over the best known approximate multiplier embedded GSF.

关键词： Adders Computer architecture Approximation algorithms Algorithm design and analysis Smoothing methods Delays Algorithm design and analysis smoothing methods adders Computer Architecture Approximation algorithms Multiplying circuits Approximate energy-efficient design delay hand-held equipment arithmetic operation

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Fast sparse 2-D DFT computation using sparse-graph alias codes

Fast sparse 2-D DFT computation using sparse-graph alias cod...

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International conference on Acoustics, Speech, and signal processing (ICASSP)

作者： Frank Ong Sameer Pawar Kannan Ramchandran Dept. of Electrical Engineering and Computer Sciences University of California Berkeley

ISBN: (纸本)9781479999897

We present a novel algorithm, named the 2D-FFAST (Two-dimensional Fast Fourier Aliasing-based Sparse Transform), to compute a sparse 2D-Discrete Fourier Transform (2D-DFT) featuring both low sample and computational complexity. The proposed algorithm is based on diverse concepts from signal processing (sub-sampling and aliasing), coding theory (sparse-graph codes) and number theory (Chinese-remainder-theorem) and generalizes the 1D-FFAST algorithm recently proposed by Pawar and Ramchandran to the 2D setting. Concretely, our proposed 2D-FFAST algorithm computes a k-sparse 2D-DFT, with a uniformly random support, of size N = N x × N y using O(k) noiseless spatial-domain measurements in O(k log k) computational time. Our results are attractive when the sparsity is sub-linear with respect to the signal dimension, that is, when k → ∞ and k/N → 0. For the case when the spatial-domain measurements are corrupted by additive noise, our 2D-FFAST framework extends to a noise-robust version of computing a 2D-DFT using O(k log 3 N) measurements in sub-linear time of O(k log 4 N). Empirically, we show that the 2D-FFAST can compute a k = 3509 sparse 2D-DFT of a 508 × 508-size phantom image using only 4.75k measurements. We also empirically evaluate the 2D-FFAST algorithm on a real-world magnetic resonance brain image using a total of 60.18% of Fourier measurements to provide an almost instant reconstruction with SNR=4.5 dB. This provides empirical evidence that the 2D-FFAST architecture is applicable to a wider class of input signals than analyzed theoretically in the paper.

关键词： Discrete Fourier transforms signal processing algorithms Algorithm design and analysis Computational complexity Computer architecture Delays Decoding

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ASIP design for Two dimensional cordic based DFT and DCT algorithms

ASIP Design for Two dimensional cordic based DFT and DCT alg...

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International econference on Computer and Knowledge Engineering (ICCKE)

作者： Mohammad Pivezhandi Mohammad Eshghi Electrical and Computer Engineering Shahid Beheshti Tehran Iran Faculty of Electrical and Computer Engineering Shahid Beheshti Tehran Iran

ISBN: (纸本)9781509035878

In this paper a cordic based Application-Specific Instruction-set Processor(ASIP) for Two dimensional Discrete Fourier Transform(DFT) and Discrete Cosine Transform(DCT) is proposed. Today, DFT performs an important role in digital signal processing, and DCT algorithm is suitable for image compression applications. Using cordic method inside these two signal processing algorithms reduces the number of memory accesses. ASIP can act as an alternative to ASIC and GPP design if it does satisfy the critical points of power consumption, total delay, manufacturing cost and productivity of those designs. Furthermore, for satisfying these parameters, two stage of utilization is performed on the basic Mano model. As a mater of fact, temporary registers and data bus are improved, RAM and cache memory are added, and the number of Functional units is increased. As a result the number of gates in the control unit is decreased about 84% in the DFT and 86% in the DCT in comparison to the Mano design. Moreover, the DFT and the DCT instructions in this design consume 3.6% and 3.86% as the number of clocks as the Mano design does. Utilization in the proposed pipeline architecture is evaluated with Register Transfer Language (RTL) codes.

关键词： Logic gates Oils Zinc Generators Productivity

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An Aerocraft Photogrammetry Position Sensing System

An Aerocraft Photogrammetry Position Sensing System

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2016 IEEE International conference on signal and image processing

作者： Tao Xu Chao Yang Bin Cai Yongli Zhu Aviation System Research Dept.System Engineering Research Institute

Landing aerial crafts, such as helicopters, on the board of naval vessels of small or medium size is a difficult and risky task for pilots since the tonnages are not large enough which makes the ships always swinging along with ocean *** the landing areas are moving all the way with six degrees of freedom ***, this mission will become dangerous and deadly when the weather is ***, we design a real-time and automatic position sensing system to track, locate and help a helicopter to land on deck safely under all weather *** the sake of practical application, we have not only adopted some ready and mature computational technologies from image processing, photogrammetry and computer vision, but also chosen some simple but effective optical elements to reduce the computational *** system is composed of camera units, image-processing unit, controlling system and fiber optical communication *** results show our system is capable of all-weather, real-time, robust and automatic landing mission.

关键词： Photogrammetry position sensing camera calibration image processing

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Real-time artefact filter for intraoperative thermographic imaging

Real-time artefact filter for intraoperative thermographic i...

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IEEE Biomedical Circuits and Systems (BIOCAS)

作者： Jens Müller Jan Müller Bill Thaute Ronald Tetzlaff Faculty of Electrical and Computer Engineering Technische Universität Dresden Dresden

ISBN: (纸本)9781509029600

En route to an intraoperative imaging system for brain surgery, a thermographic camera associated with time-resolved data analysis is used for the identification of functional areas and the detection of brain tumours. In this contribution we propose a Cellular Nonlinear Network based image processing system supporting massively-parallel and real-time processing of thermographic video data. In the current setup the system is implemented on a Xilinx Zynq FPGA and is used for the preprocessing of the raw data. The development and implementation of a digital low-pass filter for the compensation of local motion artefacts will be demonstrated as a typical application example of the freely programmable system.

关键词： Imaging Real-time systems Hardware Computer architecture Algorithm design and analysis Field programmable gate arrays signal processing algorithms

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