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检索条件"任意字段=2016 Conference on Design and Architectures for Signal and Image Processing, DASIP 2016"

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FPGA based parallel implementation of morphological filters

FPGA based parallel implementation of morphological filters

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International conference on Microelectronics, Computing and Communications (MicroCom)

作者： Debasish Mukherjee Susanta Mukhopadhyay G. P. Biswas Department of Computer Science and Engineering Indian School of Mines Dhanbad India

ISBN: (纸本)9781467366229

This paper presents a parallel algorithm and its hardware architecture for implementing 2-D gray-scale morphological operations namely dilation and erosion using rectangular flat top structuring elements. The proposed architecture supports parallel extension whereby throughput and processing frame rate is enhanced. The architecture is fully generic and runtime programmable with respect to image size and structuring elements size respectively. The main advantage of the architecture is its low latency, lower internal memory requirements, higher processing frame rate and throughput which makes it more amenable to real time applications. Additionally, it makes use of stream processing which eliminates the need for buffering image data, whereby memory overhead is minimized. The architecture has been synthesized using Xilinx design Suite 14.2 ISE and prototyped on Virtex 5 FPGA Board and verified using xilinx ISIM Simulator. The proposed architecture has been tested for images of varied gray-scale geometric dimension and the results shows satisfactory performance.

关键词： Computer architecture Hardware Parallel algorithms Field programmable gate arrays Clocks signal generators Gray-scale

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signal and image processing techniques for VLSI failure analysis

Signal and image processing techniques for VLSI failure anal...

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International conference on Informatics and Computing (ICIC)

作者： A. Boscaro S. Jacquir K. Sanchez P. Perdu S. Binczak Le2i UMR CNRS 6306 Univ. Bourgogne Franche-Comté Dijon France Centre National d'Études Spatiales Toulouse France Centre National d'Etudes Spatiales Direction des Lanceurs Paris ÃŽle-de-France FR Temasek Laboratories Nanyang Technological University Singapore

ISBN: (纸本)9781509016495

For VLSI, internal electrical measurements are key steps to solve design debug issues and to perform failure analysis. Due to multiple metal layers, active areas of the chip are only accessible from the backside of the die. The ability of optical contactless techniques to operate through the silicon substrate and the few sample preparation required have widely contributed to promote them as unavoidable tools of the defect localization workflow. Timing issue or unusual consumption can be detected by static and dynamic photon emission analysis and Electro Optical Probing. The identification of the emission spots is an essential step of the process. Due to scaling, more and more emission nodes are located within the acquisition area so that large variations of emission intensity can exist and it is difficult to recover a signal with a good signal to Noise Ratio (SNR). In this paper, automated techniques are reported to locate spots in these complex areas and to recover electrical waveforms with a good SNR. We will underline the challenge and define applications boundaries of these techniques. These techniques gives some perspectives for probing applications and allows FA community to use signal processing methods instead of expensive devices.

关键词： Laser beams Photonics Wavelet transforms Very large scale integration image segmentation Failure analysis Integrated optics

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design and implementation of a power and speed efficient carry select adder on FPGA

Design and implementation of a power and speed efficient car...

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International conference on Computing for Sustainable Global Development (INDIACom)

作者： Simarpreet Singh Chawla Swapnil Aggarwal Nidhi Goel Mantek Singh Bhatia Dept. of Electronics and Communication Engineering Delhi Technological University (Formerly DCE) INDIA Dept. of Computer Science and Technology Amity University Noida INDIA

ISBN: (纸本)9781467394178

Adders are one of the most common unit in digital systems. The speed, power and area occupied by an adder play a vital role in Digital signal processing system, image processing system, etc. Hence, they play an important role in deciding the time period of the clock, the place and route of various units comprising of the system and total power consumed by the system. In this paper, we propose a new architecture for a modified sequential high speed carry select adder. We have given emphasis on optimizing the time period of the clock and power consumed, by using the carry ahead generation technique of Carry Look Ahead Adder (CLAA) and multiplexing technique of Carry Select Adder (CSA). The proposed CSA was implemented on Virtex-7 and results were calculated using Vivado design Suite 2014.4.

关键词： Adders Multiplexing Delays Clocks Computer architecture Logic gates Power demand

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Reconfigurable floating point arithmetic components for DSP applications

Reconfigurable floating point arithmetic components for DSP ...

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IEEE India conference (INDICON)

作者： K Raghavendra Karthik K L Diwakara Reddy Chetan K Pawar K Sunitha H V Jayashree Department of Electronics and Communication Engineering PES Institute of Technology Bengaluru INDIA

ISBN: (纸本)9781509036479

This paper presents the reconfigurable floating point design of addition, subtraction, and Multiplication units which are used to design two blocks namely Fused Addition Subtraction (FAS) unit and Fused Dot Product (FDP) unit. The reconfigurable floating point addition and multiplication units are applied in the design of a Discrete Hilbert Transform Computation Unit and the FAS, FDP units are used in the design an 8-point complex Discrete Fourier Transform (DFT) unit and Inverse Discrete Fourier Transform (IDFT) unit based on the Radix-2 Decimation in Frequency (DIF) Fast Fourier Transform (FFT) algorithm. Discrete Hilbert Transform (DHT) is one of those Digital signal processing Transformations, which is applied on real valued sequences in order to obtain the analytical representation of the same. Reconfigurable architectures are designs, which can be employed for all the precision formats (Single Precision, Double Precision and Extended Precision etc.) given by the IEEE 754 standard by making minimal changes to register sizes. These components are implemented in Verilog on Virtex-6 FPGA. The synthesis results show that the reconfigurable systems designed are faster when used in DHT units and occupy significantly less area about 65% in terms of Slices compared to counterparts when used in DFT/IDFT units designed with FAS and FDP units.

关键词： Discrete Fourier transforms Computer architecture Algorithm design and analysis Random access memory Standards Fast Fourier transforms

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High-Performance FPGA Architecture for Multi-line Beamforming in Ultrasound Applications

High-Performance FPGA Architecture for Multi-line Beamformin...

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Euromicro Symposium on Digital System design

作者： Valentino Meacci Luca Bassi Stefano Ricci Enrico Boni Piero Tortoli Department of Information Engineering University of Florence Italy

Nowadays, several applications are requested to process huge amount of data with tight temporal constraints to produce "real time" results. This is the case of ultrasound (US) tomographic (B-mode) images used in diagnostics. A B-mode image is typically composed by many tens of vertical lines. Each line is calculated by the so-called beamformer (BF) that combines the echoes received from tens of small piezoelectric transducers integrated in the US probe. The BF processes massive quantity of data (several Gb/s) and is implemented in fast digital devices like the FPGAs. In the standard approach, the B-mode image is formed on a line-by-line basis, i.e. one line per pulse repetition interval (PRI). This limits the achievable image frame rate (IFR) to few tens of Hz, which is not suitable to detail fast, important phenomena like the heart valve movement. In the so-called plane-wave approach, the data needed to produce all of the B-mode image lines are acquired in a single PRI. In this case, the IFR can be in the order of kHz, but a more complex BF is needed. In this paper, we present a Multi-Line BF architecture, capable of real-time processing tens of lines per PRI. The BF was implemented in the research ultrasound system ULA-OP 256. A sample B-mode sequence obtained at IFR = 600Hz is presented.

关键词： Field programmable gate arrays Ultrasonic imaging Delays Probes Standards Array signal processing Transducers

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Optimal iris region matching and gaze point calibration for real-time eye tracking systems

Optimal iris region matching and gaze point calibration for ...

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IEEE International conference on Consumer Electronics (ICCE)

作者： Wen-Chung Kao Chun-Yi Lin Chen-Chien Hsu Chia-Yi Lee Bai-Yueh Ke Ting-Yi Su National Taiwan Normal University Taipei Taiwan

ISBN: (纸本)9781467383653

Compare with the infra-ray light gaze tracking systems, the visible light gaze tracking (VLGT) design provides new applications to consumer electronics. However, the VLGT suffers from the technical difficulties of accommodating various illumination conditions and unstable image features. These system design issues lead to the problem of low accuracy in estimating iris center location and high computational complexity. Leveraging from our previous work, we further improve the algorithm of ellipse matching for the iris region and the mapping function, whereas the average angular errors are less than 0.45° for both horizontal and vertical directions.

关键词： Iris Calibration Consumer electronics Gaze tracking conferences signal processing algorithms Particle swarm optimization

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Session 5: image tiling and denoising

Session 5: Image tiling and denoising

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conference on design and architectures for signal and image processing

作者： Bertrand Granado UPMC - LIP6 FR

Compute image processing algorithm on block or tile is a solution to realize an efficient parallelization on multi-processor system. In this session a GPU implementation of Block-Matching and 3-Dimensional filter (BM3D) denoising algorithmm is compared to a CPU implementation. Also a method to determine optimal 2D image tile sizing using constraint programming is implemented on a multi-core processor to optimize the system performance.

关键词： Noise reduction Algorithm design and analysis image processing Graphics processing units Filtering algorithms Programming Multicore processing

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Edge detection using bat algorithm

Edge detection using bat algorithm

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International conference on Computing for Sustainable Global Development (INDIACom)

作者： Rinky Dwivedi Hargun Kaur Sethi Monisha Rohilla Vaani Garg Yashika Nagpal Maharaja Surajmal Institute of Technology New Delhi INDIA

ISBN: (纸本)9781467394178

The Bat Algorithm (BA) is a bio-inspired algorithm authored by Xin-She Yang in 2010[8]. The bats use echolocation behavior, fluctuating pulse rates of ejaculation and modulation, to locate their dupe and hurdles. Same data set is also used to identify non-identical class of insects in the complete black out situation. The present research focuses on solving the Edge detection problem and for the purpose, the research inherits the concepts of Bat Algorithm (BA) from the pool of swarm intelligence algorithms. The relevance of Bat algorithm is centered on the positioning of the bats and for the current problem; the bats are directed by the confined deviations in the image's acuteness assessment. Empirical outcomes have been feathered to exhibit the attainment of the contingent approach.

关键词： image edge detection Algorithm design and analysis conferences Particle swarm optimization signal processing algorithms Electronic mail Heuristic algorithms

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Object Recognition from Human Tactile image Using Artificial Neural Network

Object Recognition from Human Tactile Image Using Artificial...

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International conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology

作者： Somchai Pohtongkam Jakkree Srinonchat Signal Processing Research Laboratory Faculty of Engineering Rajamangala University of Technology

ISBN: (纸本)9781467397506

This paper presents a recognition of images objects that are out of touch by capturing the texture of objects that existed in everyday life which sub-divided according to the different parts of the human hand palm. They are divided into sections based on the physiology of the human hand by dividing the exposure of 15,20 and 26 proportions and then analyzed. This work is the basis design of human-like hand for a robot to work effectively. These pictures of touch present the genuine sensory system of a human hand. They will be processed to characterize the touched object as the different area for the exposed surface of the object will create different for the palm's pressure. After that, we extract the features of the pressure from pressing the object and use an artificial neural network to distinguish different types of objects. The results of tests on 15 types of objects show the accurate result of the analysis of at the average maximum of 78.38% with the 26 proportions palm. This research will form the basis design of human-like hand for a robot that can recognize objects robot caught.

关键词： Human Palm Robot hand Hand Segmentation Tactile image ANN

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Comparison of four recovery algorithms used in compressed sensing for ECG signal processing

Comparison of four recovery algorithms used in compressed se...

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Computers in Cardiology (CinC)

作者： Zhimin Zhang Shoushui Wei Dingwen Wei Liping Li Feng Liu Chengyu Liu School of Control Science and Engineering Shandong University Jinan China School of data science and soft Engineering Qingdao university Qingdao China School of Science and Technology Shandong University of Traditional Chinese Medicine Jinan China School of Information Technology and Electrical Engineering University of Queensland Queensland Australia

ISBN: (纸本)9781509008964

Compressed Sensing (CS) has been used in ECG signal compressing with the rapid development of real-time & dynamic ECG applications. signal reconstruction process is an essential step in CS-based ECG processing. Many recovery algorithms have been reported in the last decades. However, the comparative study on their reconstructing performances for CS-based ECG signal processing lacks, especially in real-time applications. This study aimed to investigate this issue and provide useful information. Four typical recovery algorithms, i.e., compressed sampling matching pursuit (CoSaMP), orthogonal matching pursuit (OMP), expectation-maximum-based block sparse Bayesian learning (BSBLEM) and bound-optimization-based block sparse Bayesian learning (BSBL BO) were compared. Two performance indices, i.e., the percentage of root-mean-square difference (PRD) and the reconstructing time (RT), were tested to observe their changes with the change of compression ratio (CR). The results showed that BSBL_BO and BSBL_EM methods had better performances than OMP and CoSaMP methods. More specifically, BSBL_BO reported the best PRD results while BSBL_EM achieved the best RT index.

关键词： Electrocardiography Matching pursuit algorithms Bayes methods signal processing algorithms image reconstruction Compressed sensing Algorithm design and analysis

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