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Compact high resolution multi-aperture LWIR imaging system

Compact high resolution multi-aperture LWIR imaging system

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International conference on Industrial and Information Systems, ICIIS

作者： B. N. R. Ganesh P. Rajesh Kumar Development & Engineering Division Bharat Electronics Limited (BEL) Machilipatnam AP India Bharat Electronics Ltd Bangalore Karnataka IN

LWIR (Long Wave Infrared) imaging systems are built intensely less in size by concurrently amassing respective low resolution pictures with multi small aperture optics instead gathering a common high resolution picture with a broad aperture optics. For instance, in Thin Observation Module using Bound Optics (TOMBO) lenslets, collection of multiple small lenses is used to replace the single macro lens typically used in LWIR systems. In the TOMBO arrangement, mini lenses are the imaging elements. Proposed LWIR concept is built on a collection of focal arrays passing various portions of the complete field of view (FOV). signal processing methods are used to generate the complete picture by stitching the pictures of various arrays. A focal plane array of a thermal detector format 1024×768 is broken up into 4 squares of 512 × 384 pixels each in a 2 × 2 array. Four lenslets form four separate images of the scene on the detector, each slightly offset from the neighbor. High resolution algorithm is applied to put together a complete resolution image of the picture. The use of separate channels advantages to a less complex lens manufacturing, thus resulting in reduced fabrication cost. This paper describes the design of miniaturized LWIR-camera imaging. We also made a comparison between the conventional aperture and multi aperture imaging systems.

关键词： Lenses Apertures Cameras image resolution image reconstruction

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FPGA implementations of HEVC Inverse DCT using high-level synthesis

FPGA implementations of HEVC Inverse DCT using high-level sy...

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conference on design and architectures for signal and image processing

作者： Ercan Kalali Ilker Hamzaoglu Faculty of Engineering and Natural Sciences Sabanci University Istanbul Tuzla Turkey

High Efficiency Video Coding (HEVC), the recently developed international video compression standard, has 50% better video compression efficiency than H.264 video compression standard at the expense of significantly increased computational complexity. HEVC Inverse Discrete Cosine Transform (IDCT) algorithm accounts for 11% of the computational complexity of an HEVC video encoder. Recently, commercial and academic high-level synthesis (HLS) tools are started to be successfully used for FPGA implementations of digital signal processing algorithms. Therefore, in this paper, the first FPGA implementations of HEVC 2D IDCT algorithm using HLS tools in the literature are proposed. The proposed HEVC IDCT hardware are implemented on Xilinx FPGAs using three HLS tools; Xilinx Vivado HLS, LegUp, MATLAB Simulink HDL Coder. Using HLS tools significantly reduced the FPGA development time, and the resulting FPGA implementations achieved real-time performance. Therefore, HLS tools can be used for FPGA implementation of HEVC video encoder.

关键词： Hardware design languages Field programmable gate arrays MATLAB Standards Video compression Discrete cosine transforms

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A Key Frame Selection Algorithm Based on Sliding Window and image Features

A Key Frame Selection Algorithm Based on Sliding Window and ...

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International conference on Parallel and Distributed Systems (ICPADS)

作者： Jigang Cao Linchen Yu Mianlong Chen Xinyue Cui School of Computer China University of Geosciences Wuhan

ISBN: (纸本)9781509053827

Network traffic associated with video increases sharply, how to choose the interested information for a number of Internet users is challenging. So, technologies and applications related with video, such as video search, video fast browsing, video index and storage are in great demand. Behind these technologies and applications, a core problem is how to quickly browse massive video data and obtain the main content of the video. To solve this problem, different key frame extraction algorithms have been proposed. Due to the diversity of video content, different video have different characteristics. So the design of general video key frame extraction algorithm to solve the problem is not the reality. The main trend for the problem is to design the key frame extraction algorithm based on the characteristics of the video itself. In this article, we mainly focus on videos with edited boundaries and shot conversions. Aiming at this kind of video, we have designed and implemented video key frame extraction algorithm based on sliding window, the global feature Gist and local feature point detection algorithm SURF. In this algorithm, we use Gist feature to construct the global scene information of frames, and the SURF keypoint detection algorithm to extract local keypoints as local feature for each frame. Then, shot segmentation based on sliding window and shot merging algorithm is applied to dividing the original video into several shots. After that, we select the most representative frames in each video shot as key frames. Finally we evaluate the result of the algorithm from the subjective and objective perspective. Results show that key frames extracted in the algorithm are of high quality and can basically cover the main content of the original video.

关键词： Feature extraction Algorithm design and analysis signal processing algorithms Clustering algorithms Detection algorithms image color analysis Visualization

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A combined feature representation of deep feature and hand-crafted features for person re-identification

A combined feature representation of deep feature and hand-c...

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IEEE International conference on Progress in Informatics and Computing (PIC)

作者： Youjiao Li Li Zhuo Xiaochen Hu Jing Zhang Signal & Information Processing Laboratory Beijing University of Technology Beijing China Department of Computer Science and Technology Shandong University of Technology Zibo China Collaborative Innovation Center of Electric Vehicles in Beijing Beijing China

ISBN: (纸本)9781509034857

Person re-identification is one of the hot topics in computer vision. How to design a robust feature representation to identify pedestrians is a key problem for person re-identification. In this paper, a feature representation based on Multi-Statistics Cascade on Pyramid (MSCP) is proposed for person re-identification. The MSCP feature is composed of deep PCA network feature and hand-crafted features of Local Maximal Occurrence (LOMO) feature and color correlogram. MSCP can characterize the pedestrian images precisely from both global and local views. The Cross-view Quadratic Discriminant Analysis (XQDA) is employed to learn the distance metric of MSCP features. And then a novel re-identification method based on MSCP and XQDA is achieved. Experimental results on VIPeR Dataset demonstrate that our proposed method can achieve superior identification performance compared with six state-of-art methods.

关键词： Feature extraction image color analysis Measurement Histograms Principal component analysis Robustness Lighting

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Automated Bank Note Identification System for Visually Impaired Subjects in Malaysia

Automated Bank Note Identification System for Visually Impai...

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International conference on Computer and Communication Engineering, ICCCE

作者： Rashidah Funke Olanrewaju Fajingbesi Fawwaz Eniola Shaibo Mohammed Mahmoud M. International Islamic University Malaysia International Islamic University Malaysia Kuala Lumpur Wilayah Persekutuan MY

ISBN: (纸本)9781509024285

Visually Impaired Malaysians find great difficulty in recognizing bank notes as there are no commercially available aid for her currency and not much research done in the area. A very low cost, high efficient system has been proposed to help visually impaired Malaysians identify her bank notes. This system is built around the unique color of her bank note. The system features a sound module, color sensor module and a microcontroller module. These three module offer the system a unique ability to identify Malaysian bank currency and produce audible sound of the currencies' denomination. The efficiency of the proposed solution has been properly tested on a dataset composed of consecutive randomized banknotes including both positive images (Malaysian banknotes) and negative images (Non Malaysian banknotes and plain color notes) collected under a variety of conditions. The proposed algorithm, achieves overall efficiency of 94.17% recognition rate.

关键词： Feature extraction image color analysis Algorithm design and analysis signal processing algorithms Classification algorithms Statistical analysis Neural networks

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Hybrid hierarchical search motion estimation for Video Compression

Hybrid hierarchical search motion estimation for Video Compr...

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International conference on Advances in Electrical, Electronics, Information, Communication and Bio-Informatics (AEEICB)

作者： Twinkle Sebastian J. Anitha Department of Electronics and Communication Karunya University Tamil Nadu India

ISBN: (纸本)9781467397469

There has been an increasing demand for digital video technology in various fields of telecommunication, entertainment, medicine etc. and hence the need for Video Compression. Motion estimation techniques help in better Video Compression performance by removing the temporal redundancy effectively between frames. Block based motion estimation has been widely used for video coding. One such method is the Hierarchical Search Technique for BMA. In this work, a hierarchical search approach making use of three different algorithms Full Search Algorithm, New Cross Diamond Search Algorithm and a New Three Step Search Algorithm are used. The original image is sub-sampled into additional two levels. The Full Search is performed on the highest level where the complexity is relatively low. The New Cross Diamond search algorithm and a New Three-Step Search Algorithm are used in the consecutive two levels. The results of the algorithm show better performance in terms of PSNR with reduced complexity.

关键词： Motion estimation Algorithm design and analysis Diamond signal processing algorithms Video compression Complexity theory Pattern matching

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design Concepts and Characterization of a Next Generation Clinical PET Detector

Design Concepts and Characterization of a Next Generation Cl...

引用

IEEE Nuclear Science Symposium

作者： J. W. Cates C. S. Levin School of Automotive Engineering Dalian University of Technology Dalian P. R. China

The future of positron emission tomography (PET) is systems with ultra-precise coincidence time resolution (CTR) to advance time-of-flight PET (TOF-PET) performance. Current state-of-the-art commercial PET systems have 350-800 ps full-width-at-half-maximum (FWHM) timing performance, constraining annihilation events to lie somewhere within a 5-12 cm region along system detector response lines (LORs). This constraint is applied during the image reconstruction process to enhance image SNR for improved lesion detectability, increased accuracy and precision of lesion uptake measurements, less sensitivity to errors in data correction techniques (normalization, scatter, and attenuation corrections), lower injected dose, or shorter scan time. The effect of these improvements on image quality and accuracy scales with system CTR performance, and a long-standing milestone for the TOF-PET community is to drive system CTR towards 100 ps FWHM (1.5 cm localization along LORs). At this level of performance, a factor of five improvement in SNR can be realized compared to non-TOF imaging, with a transformational impact on quantitative PET imaging in many count starved and contrast-limited scenarios. Traditional PET detector designs are not able to achieve this level of CTR performance, and thus new detector concepts and signal processing methods should be explored to advance system CTR

关键词： Crystals Detectors Photonics Delays Positron emission tomography Multiplexing

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Scalable design of SDN controllers for optical networks using federation-based architectures

Scalable design of SDN controllers for optical networks usin...

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European conference on Networks and Optical Communications (NOC)

作者： João Santos Coriant R&D Portugal Amadora Portugal

The introduction of software-defined networking (SDN) principles in the optical communications ecosystem promises to change the way things are done nowadays. Although many of these principles still require proper maturation, the main premises behind SDN are quite attractive: 1) The separation of control and data plane will ultimately result in simpler hardware elements in the network with the network intelligence all concentrated in software controllers; 2) With this separation, the control plane is relieved of the hardware limitations intrinsic to the network equipment. This eases the creation of automated and virtualized functions at the controller where capacity can be added; 3) Open and standardized interfaces between applications, controllers, and network elements is going to promote innovation, interoperability and disaggregated systems. In this context, the network controller, whose main responsibility lies in the efficient configuration of the network equipment, is a crucial element to the SDN architecture. Typically, such controllers are centralized elements that detain the complete knowledge of the network. However, for large-sized networks, such concentration can lead to lengthier operations, heavier resiliency schemes, and availability of excessive storage and processing capacity. To obviate these issues and promote scalability, this paper presents a new controller architecture based on a federation of multiple sub-network controllers, each managing only a section of the network, conveniently coordinated by a hierarchically-superior controller. A clustering algorithm, based on single-linkage, is developed to create sub-networks under different grouping policies. In order to assess the impact of employing the federated approach in an optical network, we use a reference topology to determine the amount of routed demands and regeneration cards required. The results obtained show that the performance of the federated architecture can only resemble that of th

关键词： Computer architecture Clustering algorithms Repeaters Routing Optical fiber networks signal to noise ratio

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低功耗之模組化排序單元設計

低功耗之模組化排序單元設計

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作者：林郁寧成功大學

学位级别：碩士

在资料探勘、数位讯号处理、型态辨识或影像处理等的领域中，排序已广泛的被使用且是不可或缺的一项运算，且在许多应用上，往往只需要使用到极值，故探讨如何有效率的找到极值是十分重要的。此外，对於许多需要即时处理的应用来说，即... 详细信息

在资料探勘、数位讯号处理、型态辨识或影像处理等的领域中，排序已广泛的被使用且是不可或缺的一项运算，且在许多应用上，往往只需要使用到极值，故探讨如何有效率的找到极值是十分重要的。此外，对於许多需要即时处理的应用来说，即时排序的硬体实现是不可或缺的。在本论文中，我们针对排序单元提出一个有效的硬体架构，其电路架构使用索引值以及门槛值的机制，并使用模组化的方法设计，使得整个架构容易被重复使用与平行化，藉由以上设计来达到低功耗消耗的设计，最後，提出一个迭代的架构，使得整个设计能够更有效率的被使用在不同应用上。一般的排序方法，对於一些需要较大样本宽度或较多输入值的应用来说，在电路上可能需要更多的讯号传递，或是互相交换值，而造成更多的动态功率消耗。为了解决上述的问题，我们在电路架构设计上采用了较少位元所组成的索引值以及门槛值的概念，使储存的样本值不需要进行移动排序，而仅需改变索引值来完成排序。此外，进行较大输入量的迭代运算时，利用门槛值来排除掉不必要的数值以降低重复运算的次数，如此就可有效减少电路中讯号的传递以及运算次数，藉此达到节省功率消耗的结果，此外，我们亦针对控制电路的设计以逻辑最佳化的化简方法来实现，大幅改善整体硬体成本使用。实验结果显示我们和其他文献电路架构相比，此电路的功率消耗平均仅约一半，但需要一些额外的面积代价。此论文中，所有的硬体架构之实现是使用Verilog硬体描述语言，电路合成是利用Synopsys design Vision以及TSMC的标准元件库，最後采用Synopsys Power Compiler量测电路布局後模拟的功率消耗。依据合成结果与功率消耗量测，我们所提出的电路架构设计在低功率消耗上具有极佳的竞争力。

关键词：硬體架構排序單元邏輯最佳化迭代運算低功率

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Evaluation of analog and digital signal processing on PSoC architecture with DCT as use case: Comparison of an analog and software based implementation of the digital cosine transform on a Programmable System on Chip

Evaluation of analog and digital signal processing on PSoC a...

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conference on design and architectures for signal and image processing

作者： Stephan Werner Bernhard Stiehle Jürgen Becker Karlsruhe Institute of Technology (KIT) Institute for Information Processing Technologies (ITIV) Karlsruhe Germany

One trend for signal processing hardware is the increasing integration of different functionalities in one mixed-signal chip. But the additional integration of analog components on one chip with digital components and a micro-processor like in the Programmable System on Chip (PSoC) from Cypress is accompanied with the extension of the design space and the need to explore it by evaluating different implementations with the same functionality to find a good trade-off between analog and digital signal processing. This paper evaluates different implementations of the discrete cosine transform (DCT) with different analog-digital partitioning. Therefore the DCT is integrated as software controlled analog circuit based on the switched capacitors and operational amplifiers available in the analog subsystem of the PSoC architecture. The presented analog DCT implementation scales linear and the number of simultaneously computable spectral signal components is only limited by the available on-chip resources on the currently used PSoC5LP. To evaluate the analog implementation, the DCT is also implemented as software executed on the ARM Cortex-M3 integrated in the PSoC5LP. The comparison of both solutions shows that the analog hardware available on the PSoC architecture can be used to directly process analog sensor signals with only minor additional off-chip components with a CPU load of about 8% caused by the software controlling the analog subsystem.

关键词： Discrete cosine transforms Software Capacitors Computer architecture System-on-chip Hardware Electronics packaging

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