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Robot navigation based on an efficient combination of an extended A∗ algorithm, bird's eye view and image stitching

Robot navigation based on an efficient combination of an ext...

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conference on design and architectures for signal and image processing

作者： Jens Rettkowski David Gburek Diana Göhringer Application-Specific Multi-Core Architectures (MCA) Group Ruhr-University Bochum (RUB) Germany

Robotics combines a lot of different domains with sophisticated challenges such as computer vision, motion control and search algorithms. Search algorithms can be applied to calculate movements. The A* algorithm is a well-known and proved search algorithm to find a path within a graph. This paper presents an extended A* algorithm that is optimized for robot navigation using a bird's eye view as a map that is dynamically generated by image stitching. The scenario is a robot that moves to a target in an environment containing obstacles. The robot is controlled by a Xilinx Zynq platform that contains an ARM processor and an FPGA. In order to exploit the flexibility of such an architecture, the FPGA is used to execute the most compute-intensive task of the extended A* algorithm. This task is responsible for sorting the accessible nodes in the graph. Several environments with different complexity levels are used to evaluate the extended A* algorithm. The environment is captured by a Kinect sensor located directly on the robot. In order to dewarp the robot's view, the frames are transformed to a bird's eye view. In addition, a wider viewing range is achieved by image stitching. The evaluation of the extended A* algorithm shows a significant improvement in terms of memory utilization. Accordingly, this algorithm is especially practicable for embedded systems since they have often only limited memory resources. Moreover, the overall execution time for several use cases is reduced up to a speed-up of 2.88x.

关键词： Heuristic algorithms Navigation Cameras Robot vision systems Path planning

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Worst-case latency analysis of SDF-based parametrized dataflow MoCs

Worst-case latency analysis of SDF-based parametrized datafl...

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conference on design and architectures for signal and image processing

作者： Mladen Skelin Marc Geilen Francky Catthoor Sverre Hendseth Norwegian University of Science and Technology Eindhoven University of Technology MEC vzw

Modern-day streaming digital signal processing (DSP) applications are often accompanied by real-time requirements. In addition, they expose increasing levels of dynamic behavior. Dynamic dataflow models of computation (MoCs) have been introduced to model and analyze such applications. Parametrized dataflow MoCs are an important subclass of dynamic dataflow MoCs because they integrate dynamic parameters and run-time adaptation of parameters in a structured way. However, these MoCs have been primarily analyzed for functional behavior and correctness while the analysis of their temporal behavior has received little attention. In this work, we present a new analysis approach that allows analysis of worst-case latency for dynamic streaming DSP applications that can be captured using parametrized dataflow MoCs based on synchronous dataflow (SDF). We show that in the presence of parameter inter-dependencies our technique can yield tighter worst-case latency estimates than the existing techniques that operate on SDF structures that abstract the worst-case behaviour of the initial parametrized specifications. We base the approach on the (max,+) algebraic semantics of timed SDF and on its non-parametric generalization known as FSM-based scenario-aware dataflow (FSM-SADF). We evaluate the approach on a realistic case study from the multimedia domain.

关键词： Decoding Delays Digital signal processing Computational modeling Multimedia communication Adaptation models Streaming media

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MCAPI-compliant Hardware Buffer Manager Mechanism to Support Communication in Multi-Core architectures

MCAPI-compliant Hardware Buffer Manager Mechanism to Support...

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design, Automation & Test in Europe conference & Exhibition

作者： Thiago Raupp da Rosa Thomas Mesquida Romain Lemaire Fabien Clermidy Univ. Grenoble Alpes F-38000 France

ISBN: (纸本)9781467392280

High performance and high power efficiency are two mandatory constraints for multi-core systems in order to successfully handle the most recent applications in several fields, e.g. image processing and communication standards. Nowadays, hardware accelerators are often used along with several processing cores to achieve the desired performance while keeping high power efficiency. However, such systems impose an increased programming complexity due to the lack of software standards that supports heterogeneity, frequently leading to custom solutions. On the other hand, implementing a standard software solution for embedded systems might induce significant overheads. This work presents a hardware mechanism in codesign with a standard programming interface (API) for embedded systems focusing to decrease overheads imposed by software implementation while increasing programmability and communication performance. The results show gains of up to 97% in latency and an increase of 40 times in throughput for synthetic traffics and an average decrease of 95% in communication time for an image processing application.

关键词： MCAPI-compliant Hardware Buffer Manager Mechanism Support Communication Multi-Core architectures

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The Study of the Indoor Positioning Based on Smart Wearable Technologies

The Study of the Indoor Positioning Based on Smart Wearable ...

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2016 IEEE International conference on signal and image processing

作者： Wun-Ye Ku Yi-Shin Liou Chih-Yu Yang Ming-Yih Lee Chung-Chih Lin Wen-Yen Lin Tsai-Hsuan Tsai Computer Science and Information Engineering Healthy Aging Research Center Chang Gung University Graduate Institute of Medical Mechatronics Chang Gung University Department of Neurosurgery Chang Gung Memorial Hospital Department of Electrical Engineering Chang Gung University Department of Industrial Design Chang Gung University

we design a low energy Bluetooth(BLE) device including reference-tag-based indoor position algorithm to solve different situations including location determining, route guideline and tracking in this *** can not only help the visitor or patient to understand the position but also provide a system for medical staff to monitor the safety of patients and new born babies in *** device is tiny enough to be embedded into visitor's wristband, baby's foot band and patient's *** is composed of signal control unit, signal sensing unit and wireless connection *** signal control unit is responsible to control and memorize the status of the device by an ultra-low power MCU and an EEPROM memory *** signal sensing unit is a motion tracking sensor module to capture the accelerometer *** wireless connection unit combined of beacon and Bluetooth module to send data package as a BLE *** indoor location-based services(LBS) system is combined with smart beacon and Wi-Fi *** plays the role of client and Wi-Fi gateway is *** RSSI(Received signal Strength Indicator) of BLE signal to determine whether the beacon owner is in a particular ***, there may be two or more Wi-Fi gateways to receive the same beacon signal in the same time, we add a reference beacon to each Wi-Fi gateway to reduce the error rate of determining beacon's *** result of experim ent shows that there is only 5% error rate for determining the position of devices.

关键词： smart wearable device wireless beacon indoor positioning

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An Efficient FPGA and KBNN Based Training and Classification System for the Implementation of VLSI Architecture

An Efficient FPGA and KBNN Based Training and Classification...

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International conference on Wireless Communications, signal processing and Networking

作者： K. Arunakumari I. Rexiline Sheeba Dept. of Electronics and Communication Engg. Sathyabama University Chennai India Dept. of Electronics and Communication Engg Sathyabama University Chennai India

ISBN: (纸本)9781467393393

The Field Programmable Gate Array (FPGA) technology is widely used in various applications such as Digital image processing (DIP), Digital signal processing (DSP), data processing, etc. As the active and the passive components are fabricated in a single chip the performance level of the applications, the overall speed, area, and power of the application systems can be minimized effectively. The identification of the circuit information is an important process in the Very Large Scale Integration (VLSI) design. The existing architectures such as neural network, and brute force approach, etc., improve the analytical model work and refine the model using the trial and error method. The use of these existing techniques for the circuit information identification is inefficient, inaccurate, highly complex, time consuming, power consuming, and produced minimal classification result quality. To address these issues we have proposed a FPGA based VLSI architecture. The proposed architecture collects the feature values of the circuit manually. The collected features are then applied the Discrete Fourier Transform (DFT) based feature extraction process for identifying the information for the required data base and the input selected circuit details. The classification process is performed using the Knowledge Based Neural Network (KBNN). The performance of the proposed architecture is compared with the existing neural network methodology. The comparison results show that the suggested architecture increases the speed, reduces the overall power consumption, overall delay time, and also improves the circuit details classification speed level.

关键词： Very Large Scale Integration (VLSI) Field Programmable Gate Array (FPGA) Discrete Fourier Transform (DFT) Knowledge Based Neural Network (KBNN) Digital image processing (DIP) Digital signal processing (DSP)

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Reduction of Non-White Noise from Hyperspectral images Based on Tensor Decomposition

Reduction of Non-White Noise from Hyperspectral Images Based...

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2016 IEEE 13th International conference on signal processing（ICSP2016）

作者： Jiwei LIU Min FU Xuefeng LIU College of Design Art Shenyang Aerospace University College of Information Science & Engineering Ocean University of China College of Automation & Electronic Engineering Qingdao University of Science & Technology

Acquired images in hyperspectral imagery are disturbed by additive noise which is usually assumes as zeromean white one. In fact, there is still non-white noise in hyperspectral images(HSIs). The 2-dimensional filtering methods and multidimensional tensor decomposition algorithms cannot be used to remove non-white noise from HSIs directly. Therefore, a prewhitening denoising solution based on tensor decomposition is proposed in this paper. The prewhitening procedure can help to transform the non-white noise into a white one and the tensor decomposition method removes the noise without affecting the related information between image planes. The simulation results show that this non-white noise reducing approach has promising prospects in this field compared to existing denoising methods.

关键词： Denoising Parallel Factor Analysis(PARAFAC) Multidimensional Wiener Filtering(MWF) HSI

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Building a research data science platform from industrial machines

Building a research data science platform from industrial ma...

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IEEE International conference on Big Data

作者： Fang Cherry Liu Fu Shen Duen Horng Chau Neil Bright Mehmet Belgin Partnership for An Advanced Computing Environment (PACE) Georgia Institute of Technology Atlanta Georgia School of Computational Science and Engineering Georgia Institute of Technology Atlanta Georgia

ISBN: (纸本)9781467390064

Data Science research has a long history in academia which spans from large-scale data management, to data mining and data analysis using technologies from database management systems (DBMS's). While traditional HPC offers tools on leveraging existing technologies with data processing needs, the large volume of data and the speed of data generation pose significant challenges. Using the Hadoop platform and tools built on top of it drew immense interest from academia after it gained success in industry. Georgia Institute of Technology received a donation of 200 compute nodes from Yahoo. Turning these industrial machines into a research Data Science Platform (DSP) poses unique challenges, such as: nontrivial hardware design decisions, configuration tool choices, node integration into existing HPC infrastructure, partitioning resource to meet different application needs, software stack choices, etc. We have 40 nodes up and running, 24 running as a Hadoop and Spark cluster, 12 running as a HBase and OpenTSDB cluster, the others running as service nodes. We successfully tested it against Spark Machine Learning algorithms using a 88GB image dataset, Spark DataFrame and GraphFrame with a Wikipedia dataset, and Hadoop MapReduce wordcount on a 300GB dataset. The OpenTSDB cluster is for real-time time series data ingestion and storage for sensor data. We are working on bringing up more nodes. We share our first-hand experience gained in our journey, which we believe will benefit and inspire other academic institutions.

关键词： Hardware Sparks Digital signal processing Ecosystems Distributed databases Cloud computing

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Proceedings of the International conference on Parallel processing Workshops

Proceedings of the International Conference on Parallel Proc...

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44th Annual conference of the International conference on Parallel processing Workshops, ICPPW 2015

ISBN: (纸本)9781467375894

The proceedings contain 35 papers. The topics discussed include: side effect mitigation algorithm for cache maintenance in opportunistic networks;simple floor plan construction via cloudsourcing;using open edX forum for supporting collaborative learning;towards an automatic prediction of image processing algorithms performances on embedded heterogeneous architectures;multi-core approach towards efficient biometric cryptosystems;sparse matrix sparse vector multiplication - a novel approach;thread-level value speculation for image-processing applications;a special sorting method for neighbor search procedure in smoothed particle hydrodynamics on GPUs;the design and implementation of embedded online laboratory;and spatial join query processing in cloud: analyzing design choices and performance comparisons.

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Real-time correlation for locating systems utilizing heterogeneous computing architectures

Real-time correlation for locating systems utilizing heterog...

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conference on design and architectures for signal and image processing

作者： Marc Reichenbach Max Kasparek Mohammad Alawieh Konrad Häublein Dietmar Fey Department Computer Science Friedrich-Alexander-Universitat Erlangen-Niirnberg (FAU) Fraunhofer Institut fur integrierte Schaltungen (IIS)

The usage of locating systems in sports (e.g. soccer) elevates match and training analysis to a new level. By tracking players and balls during matches or training, the performance of players can be analyzed, the training can be adapted and new strategies can be developed. The radio-based RedFIR system equips players and the ball with miniaturized transmitters, while antennas distributed around the playing field receive the transmitted radio signals. A cluster computer processes these signals to determine the exact positions based on the signals' Time Of Arrival (TOA) at the back end. While such a system works well, it is neither scalable nor inexpensive due to the required computing cluster. Also the relatively high power consumption of the GPU-based cluster is suboptimal. Moreover, high speed interconnects between the antennas and the cluster computers introduce additional costs and increase the installation effort. However, a significant portion of the computing performance is not required for the synthesis of the received data, but for the calculation of the unique TOA values of every receiver line. Therefore, in this paper we propose a smart sensor approach: By integrating some intelligence into the antenna (smart antenna), each antenna can correlate the received signal independently of the remaining system and only TOA values are send to the backend. While the idea is quite simple, the question of a well suited computer architecture to fulfill this task inside the smart antenna is more complex. Therefore, we are evaluating embedded architectures, such as FPGAs, ARM cores as well as a many core CPU (Epiphany) for this approach. Thereby, we are able to achieve 50.000 correlations per second in each smart antenna. As a result, the backend becomes lightweight, cheaper interconnects through data reduction are required and the system becomes more scalable, since most processing power is already included in the antenna.

关键词： Computer architecture Correlation Antennas Field programmable gate arrays Intelligent sensors Receivers Hardware

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A Cross Layer design for Performance Enhancements in LTE-A System

A Cross Layer Design for Performance Enhancements in LTE-A S...

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International conference on Wireless Communications, signal processing and Networking

作者： V. Sharmila Gandhi B. Maheswaran Department of ECE Mepco Schlenk Engineering College Sivakasi India

ISBN: (纸本)9781467393393

Cross-layer design with respect to reference layered architecture is the design of algorithms, protocols and architectures that utilize an available set of interlayer exchanges a superset of the standard interfaces provided by the reference layered architecture. The cross layer approach transports feedback, dynamically via the layer margins to enable the remuneration for e.g. load, latency or other mismatch of requirements and resources by any deal with input to an additional layer. In the original OSI networking model, Layered communication approaches typically separate communication responsibilities into several layers, with a patent definition of the functionality of each layer. Cross layer optimization removes such strict restrictions to permit communication between layers to restore information and enable interfaces. For example, having knowledge of the existing physical condition will help a channel distribution offer at the MAC level in optimizing tradeoffs and achieve throughput maximization. The paper "A Cross Layer design for Performance Enhancement in LTE-A Systems" consists of four steps: i) Analyze the Various Optimization Techniques ii) Parameters Abstraction iii) Cross Layer Optimization iv) Performance Evaluation.

关键词： Automatic Repeat Request Long Term Evolution Advanced

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