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Energy and Execution Time Comparison of Optical Flow Algorithms on SIMD and GPU architectures 12

Energy and Execution Time Comparison of Optical Flow Algorit...

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12th conference on design and architectures for signal and image processing (dasip)

作者： Petreto, Andrea Hennequin, Arthur Koehler, Thomas Romera, Thomas Fargeix, Yohan Gaillard, Boris Bouyer, Manuel Meunier, Quentin L. Lacassagne, Lionel Sorbonne Univ CNRS LIP6 F-75005 Paris France Lheritier Alcen F-95862 Cergy Pontoise France

ISBN: (纸本)9781538682371

This article presents and compares optimized implementations of two optical flow algorithms on several target boards comprising multi-core SIMD processors and GPUs. The two algorithms are Horn-Schunck (HS) and TV-L1, and have been chosen because they are both well-known, and because of their different computational complexity and accuracy. For both algorithms, we have made parallel optimized SIMD implementations, while HS has also been implemented on GPUs. For each algorithm, the comparison between the different versions and target boards is carried out in a two-dimensional fashion: in terms of computing speed-in order to achieve real-time computation-and in terms of energy consumption since we target embedded systems. The results show that for HS, the GPUs are the most efficient in both dimensions, able to process in realtime performances (25 frames per second) up to 8Mpix images for 0.35J per image, against 1.8Mpix images for 0.24J per image on CPU. The results also highlight the impact of optimizations on TV-L1: far slower than HS without optimization, it can almost match its performance after optimization on CPU, and can achieve real-time performances with 0.25J for 1.4Mpix images. We hope these results will help developers design optical flow embedded systems.

关键词： Optimization Graphics processing units Optical imaging Computer architecture Real-time systems Embedded systems Power demand

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Application of temporal decoupling to the creation of efficient performance models of automotive architectures

Application of temporal decoupling to the creation of effici...

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6th Annual conference on design and architectures for signal and image processing, dasip 2012

作者： Majdoub, Takieddine Le Nours, Sebastien Pasquier, Olivier Nouvel, Fabienne Univ Nantes IETR UMR 6164 Polytech-Nantes rue C. Pauc Nantes F-44000 France INSA Rennes IETR UMR 6164 20 avenue des Buttes de Coësmes 35043 Rennes France

ISBN: (纸本)9782953998726

Due to the increasing complexity of communication infrastructures in the automotive domain, reliable models of embedded system architectures are necessary in order to assist designers in the development process. In this context, transaction level modeling, supported by languages as SystemC, is a promising solution to allow performances of networked architectures to be assessed with different compromise between accuracy and simulation speed. In this paper, a modeling technique is proposed to improve the simulation speed of architecture models used for performance evaluation. A specific case study inspired from the automotive domain is used to illustrate how simulation speed-up is achieved using the proposed technique. A significant simulation speed up by an order of magnitude of 100 is achieved in the considered case study. © 2012 ECSI.

关键词： Modeling languages

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Implementation of a real-time image-based vibration detection and adaptive filtering on an FPGA 12

Implementation of a real-time image-based vibration detectio...

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12th conference on design and architectures for signal and image processing (dasip)

作者： Uetsuhara, Kazuya Tahara, Akanae Manabe, Taito Shibata, Yuichiro Nagasaki Univ Grad Sch Engn Nagasaki Japan

ISBN: (纸本)9781538682371

In this paper, we propose and implement a field-programmable gate array (FPGA) system which extracts a vibration component of a desired frequency band from moving images in real-time, aiming at application to image-based vibration suppression such as microsurgery assistance systems. The technical challenges to this end are two-fold: fast and robust detection of vibration components in given moving images and zero-phase band-pass filtering for a desired frequency band. For the former, we employ a statistical approach using dense optical flow to derive frequency components, and design a custom optical flow computing hardware with the Lucas-Kanade (LK) method. For the latter, we implement a sort of adaptive band-pass filters called a bandlimited multiple Fourier linear combiner (BMFLC), which can recompose input signals as a mixture of sinusoidal signals with multiple frequencies in a band with no phase delay. Both designs are implemented in a deeply pipelined manner on a Xilinx Kintex-7 XC325T FPGA, without using any external memories. Empirical experiments reveal that the proposed system extracts a vibration component of high-frequency tremors in hand motions, while intentional low-frequency motions are successfully filtered out. The system processes VGA moving images at 60 fps, with a delay of less than 1 us for the BMFLC, suggesting effectiveness of the deep pipelined architecture.

关键词： Optical imaging Optical attenuators Vibrations Optical sensors Real-time systems Surgery Field programmable gate arrays

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Flexible VLIW processor based on FPGA for real-time image processing

Flexible VLIW processor based on FPGA for real-time image pr...

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2011 conference on design and architectures for signal and image processing, dasip 2011

作者： Brost, Vincent Meunier, Charles Saptono, Debyo Yang, Fan LE2I-CNRS 5158 Laboratory University of Burgundy 21078 Dijon France

ISBN: (纸本)9781457706196

Modern FPGA chips, with their larger memory capacity and reconfigurability potential, are opening new frontiers in rapid prototyping of embedded systems. With the advent of high density FPGAs it is now possible to implement a high performance Very Long Instruction Word (VLIW) processor core in an FPGA. With VLIW architecture, the processor effectiveness depends on the ability of compilers to provide sufficient Instruction Level Parallelism (ILP) from program code. This paper describes research result about enabling the VLIW processor model for real-time processing applications by exploiting FPGA technology. Our goals are to keep the flexibility of processors in order to shorten the development cycle, and to use the powerful FPGA resources in order to increase real-time performance. We present a flexible VLIW VHDL processor model with a variable instruction set and a customizable architecture which allow exploiting intrinsic parallelism of a target application using advanced compiler technology and implementing it in an optimal manner on FPGA. Some common algorithms of image processing were tested and validated on an FPGA Virtex-6 based board using the proposed development cycle. Our approach applies some criteria for co-design tools: flexibility, modularity, performance, and reusability. © 2011 IEEE.

关键词： Field programmable gate arrays (FPGA)

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Reconfigurable Vision processing System for Player Tracking in Indoor Sports

Reconfigurable Vision Processing System for Player Tracking ...

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conference on design and architectures for signal and image processing (dasip)

作者： Ibraheem, Omar W. Irwansyah, Arif Hagemeyer, Jens Porrmann, Mario Rueckert, Ulrich Bielefeld Univ CITEC Cognitron & Sensor Syst Grp Bielefeld Germany

ISBN: (纸本)9781538635346

In recent years, there has been an increasing growth of using vision-based systems for tracking the players in team sports to evaluate and enhance their performance. Vision-based player tracking has high computational demands since it requires processing of a huge amount of video data based on the utilization of multiple cameras with high resolution and high frame rates. In this paper, we present a reconfigurable system to track the players in indoor sports automatically without user interaction. The proposed system can process live video data streams from multiple cameras as well as offline data from recorded video files. FPGA technology is used to accelerate this player tracking system by implementing the video acquisition, video preprocessing, player segmentation, and team identification & player detection modules in hardware, realizing a real-time system. The teams are identified and the players' positions are detected based on the colors of their jerseys. The detection results are sent from the FPGA to the host-PC where the players are tracked. Our results show that the achieved average player detection rate is up to 95.5%. The proposed system can process live video data using two GigE Vision cameras with a resolution of 1392x1040 pixels and 30 fps for each camera. A speed-up of 20 is achieved compared to an OpenCV-based software implementation on a host-PC equipped with a 2.93 GHz Intel i7 CPU.

关键词： Streaming media Cameras Field programmable gate arrays IP networks image color analysis Games Target tracking

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On the scalability of image and signal processing parallel applications on emerging cc-NUMA many-cores

On the scalability of image and signal processing parallel a...

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6th Annual conference on design and architectures for signal and image processing, dasip 2012

作者： Almaless, Ghassan Wajsburt, Franck LIP6 UPMC Sorbonne Universités 4 place Jussieu Paris France

ISBN: (纸本)9782953998726

Nowadays, single-chip cache-coherent multi-cores up to 100 cores are a reality and many-cores of hundreds of cores are planned in the near future. This technological shift undertaking by the high-end computer-industry is converging with the design motivation of other domains like embedded and HPC industries. In this paper, we propose to investigate the scalability of the same four unmodified, shared-memory, image and signal processing oriented parallel applications on two targets: (i) embedded - TSAR, a single-chip 256-cores based, Cycle-Accurate-Bit-Accurate simulated, cc-NUMA many-core;and (ii) high-end - an AMD Opteron Interlagos, 64-core based, cc-NUMA many-core. Beside our scalability results on both cc-NUMA targets, our contributions include two operating system mechanisms: (i) a distributed, client/server based, scheduler design allowing the kernel to offer scalable inter-threads synchronization mechanisms;and (ii) a kernel-level memory affinity technique named Auto-Next-Touch allowing the kernel to transparently and automatically migrate physical pages in order to enforce the locality of thread's memory accesses. Although these two mechanisms are implemented and evaluated in ALMOS (Advanced Locality Management Operating System) running on the TSAR target, they remain applicable to other shared-memory operating systems. © 2012 ECSI.

关键词： image processing

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HLS-based fast design space exploration of ad hoc hardware accelerators: A key tool for MPSoC synthesis on FPGA

HLS-based fast design space exploration of ad hoc hardware a...

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6th Annual conference on design and architectures for signal and image processing, dasip 2012

作者： Corre, Youenn Hoang, Van-Trinh Diguet, Jean-Philippe Heller, Dominique Lagadec, Loic Lab-STICC Université de Bretagne Sud 56100 Lorient France Lab-STICC Université de Bretagne Occidentale 29200 Brest France

ISBN: (纸本)9782953998726

Over the last decade many academic and industrial system synthesis and codesign tools have been proposed to designers. However most of these tools are based on IP Libraries but either these libraries are incomplete or are simply not adapted to the targets and constraints. It means that something important is missing when it comes to real implementations. We address this question in this paper and propose a flexible, fast and practical solution. We use high level synthesis (HLS) to obtain fast estimations of hardware accelerators that can then be embedded within the loop of a larger design space exploration flow. Once some solutions are selected they can be directly reuse to synthesise and produce real IPs. In this paper we present the approach and the tool as a key component of our heterogeneous multiprocessor synthesis framework. © 2012 ECSI.

关键词： High level synthesis

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Embedded Fluorescence Lifetime Determination for High Throughput Real-Time Droplet Sorting with Microfluidics

Embedded Fluorescence Lifetime Determination for High Throug...

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conference on design and architectures for signal and image processing (dasip)

作者： Lieske, Tobias Uhring, Wilfried Dumas, Norbert Leonard, Jeremie Fey, Dietmar Friedrich Alexander Univ Erlangen Nurnberg FAU Dept Comp Sci Chair Comp Architecture Erlangen Germany Univ Strasbourg ICube Strasbourg France CNRS Paris France Univ Strasbourg IPCMS Strasbourg France

ISBN: (纸本)9781538635346

Time-resolved fluorescence (TRF) analysis is considered to be among the primary research tools in biochemistry and biophysics. One application of this method is the investigation of biomolecular interactions with promising applications for biosensing. For the latter context, time-correlated single photon counting (TCSPC) is the most sensitive, hence preferred implementation of TRF. However, high throughput applications are presently limited by the maximum achievable photon acquisition rate, and even more by the data processing rate. The latter rate is actually limited by the computational complexity to estimate accurately the fluorescence lifetime from TCSPC data. Here we propose a solution that would enable the implementation of TRF detection for fluorescence-activated droplet sorting (FADS), a particularly high throughput, microfluidic-based technology. Most fluorescence lifetime algorithms require a large number of detected photons for an accurate lifetime computation. This paper presents an implementation based on a maximum likelihood estimator (MLE), enabling high precision estimation with a limited number of detected photons, significantly reducing the total measurement time. This speedup rapidly increases the input data rate. As a result, off-the-shelf embedded products cannot handle the data rates produced by current TCSPC units that are used to measure the fluorescence. Therefore, a configurable real-time capable hardware architecture is implemented on a field programmable gate array (FPGA) that can handle the data rates of future TCSPC units, rendering high throughput droplet sorting with microfluidics possible.

关键词： FPGA time-resolved fluorescence fluorescence lifetime microfluidics embedded signal processing

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Dataflow program analysis and refactoring techniques for design space exploration: MPEG-4 AVC/H.264 decoder implementation case study

Dataflow program analysis and refactoring techniques for des...

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2013 7th conference on design and architectures for signal and image processing, dasip 2013

作者： Ab Rahman, Ab Al-Hadi Casale Brunet, Simone Alberti, Claudio Mattavelli, Marco SCI-STI-MM École Polytechnique Fédérale de Lausanne Switzerland

ISBN: (纸本)9791092279016

This paper presents a methodology to perform design space exploration of complex signal processing systems implemented using the CAL dataflow language. In the course of space exploration, critical path in dataflow programs is first presented, and then analyzed using a new strategy for computational load reduction. These techniques, together with detecting design bottlenecks, point to the most efficient optimization directions in a complex network. Following these analysis, several new refactoring techniques are introduced and applied on the dataflow program in order to obtain feasible design points in the exploration space. For a MPEG-4 AVC/H.264 decoder software and hardware implementation, the multi-dimensional space can be explored effectively for throughput, resource, and frequency, with real-time decoding range from QCIF to HD resolutions.

关键词： Space research

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A Scalable Hardware Architecture for Retinal Blood Vessel Detection in High Resolution Fundus images 8

A Scalable Hardware Architecture for Retinal Blood Vessel De...

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8th conference on design and architectures for signal and image processing (dasip)

作者： Bendaoudi, Hamza Cheriet, Farida Ben Tahar, Houssem Langlois, J. M. Pierre Polytech Montreal Dept Comp & Software Engn Montreal PQ Canada Diagnos Inc Brossard PQ Canada

ISBN: (纸本)9791092279061

Blood vessel detection from high resolution fundus images is a necessary step in several medical applications. Automatic blood vessels detection is a computing intensive task which raises the need for accelerated hardware architectures. In this paper, we propose a scalable hardware architecture for blood vessel detection using a matched filter (MF). The algorithm is made hardware friendly using parallel processing and efficient resources sharing to achieve real-time performances. The paper also introduces a tool for the automatic generation of an HDL description based on the proposed architecture as a template. The tool takes as input the parameters of the filter to deal with the parameter selection problem and to make their choice more flexible. Performances in terms of area utilization and maximum frequency are reported. Several designs were verified and implemented on an FPGA platform. The results show significant improvements over the state of the art implementations, up to a factor of 10x for high resolution fundus images.

关键词： Retinal blood vessels detection Hardware acceleration Scalable hardware architectures

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