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conference on design and architectures for signal and image processing (dasip)

作者： Tchendjou, Ghislain Takam Alhakim, Rshdee Simeu, Emmanuel Univ Grenoble Alpes TIMA F-38000 Grenoble France CNRS TIMA F-38000 Grenoble France

ISBN: (纸本)9791092279153

This paper presents a novel methodology of objective image quality assessment (IQA) based on Fuzzy Logic (FL) method. The main purpose is to automatically assess the quality of image in agreement with human visual perception. The used attributes (quality metrics) and evaluation criteria (human rating mean opinion score MOS) are extracted from image quality database TID2013. The fuzzy model design starts by selecting the most independent attributes, by applying Pearson's correlation approach and seeking the most correlated metrics with the corresponding MOS. Then, Adaptive Neuro-Fuzzy Inference System (ANFIS) is applied in order to construct an objective fuzzy model able to efficiently predict the image quality correlated with the subjective MOS. In this paper, different fuzzy models are produced by modifying certain ANFIS configurations. After that, we select the appropriate ANFIS model that provides high prediction accuracy and stability with taking into account its implementation complexity. The overall architecture of the selected FL model consists of four input metrics, two bell-shaped membership functions associated to each input metric, two fuzzy if-then rules, two linear combination equations and one output which gives the image adequate quality score. Finally the performance of the proposed fuzzy model is compared with other IQA models produced by different machine learning methods, the simulation results demonstrate that the fuzzy logic model has a high stable behavior with the best agreement with human visual perception.

关键词： image Quality Assessment Machine Learning Fuzzy Logic Fuzzy Inference System ANFIS

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Hardware-software implementation of vehicle detection and counting using virtual detection lines 8

Hardware-software implementation of vehicle detection and co...

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8th conference on design and architectures for signal and image processing (dasip)

作者： Kryjak, Tomasz Komorkiewicz, Mateusz Gorgon, Marek AGH Univ Sci & Technol Fac Elect Engn Automat Comp Sci & Biomed Engn Dept Automat & Biomed Engn Al Mickiewicza 30 PL-30059 Krakow Poland

ISBN: (纸本)9791092279061

In this paper a hardware-software system for vehicle detection and counting at intersections is presented. It has been implemented and evaluated on the heterogeneous Zynq platform. The vehicle detection is based on the concept of virtual detection lines (VDL). Differences in colour, horizontal edges and Census transform results between areas around the VDL for two consecutive frames are used to disclosure particular vehicles. This part of the system is designed in hardware description language and implemented in the reconfigurable resources of the Zynq platform. Information about the vehicle presence, along with the time-spatial image obtained at the VDL are transmitted and processed on the ARM core integrated in the Zynq device. This allows to perform further analysis and eliminate false or multiple detections. The solution has been evaluated on several video sequences recorded in various conditions: sunny day (the occurrence of deep shadows), cloudy day, rain and night-time. The system could be an important element of an intelligent transportation system (ITS) i. e. applied in a smart camera.

关键词： Vehicle detection Smart cameras Intelligent transportation systems Video sequences Hardware design languages software implementation Virtual Intersection False

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Synthesis of arithmetic expressions for the fixed-point arithmetic: The Sardana approach

Synthesis of arithmetic expressions for the fixed-point arit...

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6th Annual conference on design and architectures for signal and image processing, dasip 2012

作者： Ioualalen, Arnault Martel, Matthieu Univ. Perpignan Via Domitia Digits Architectures et Logiciels Informatiques F-66860 Perpignan France Univ. Montpellier II Laboratoire d'Informatique Robotique et de Microelectronique de Montpellier UMR 5506 F-34095 Montpellier France CNRS Laboratoire d'Informatique Robotique et de Microelectronique de Montpellier UMR 5506 F-34095 Montpellier France

ISBN: (纸本)9782953998726

Sardana is a tool which optimizes the arithmetic expressions present in source codes. The optimization is done by synthesizing automatically new mathematically equal expressions, given ranges of values for the variables. In previous work, Sardana has been used to optimize the numerical accuracy of floating-point expressions, by minimizing the worst roundoff error on the result of the evaluation. In this article, we show how our tool can be used to synthesize arithmetic expressions optimized for the fixed-point arithmetic. In this context, Sardana minimizes the number of bits required to represent without overflow the integer parts of the fixed-point numbers possibly occurring at any stage of the evaluation of an expression. We present experimental results showing how our tool optimizes the implementation of digital filters commonly used in image processing. © 2012 ECSI.

关键词： Fixed point arithmetic

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FPGA based real-time on-road stereo vision system

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JOURNAL OF SYSTEMS ARCHITECTURE 2017年 81卷 32-43页

作者： Dehnavi, M. Eshghi, M. Shahid Beheshti Univ EE Dept Tehran *** Iran

Accurate and Real-Time stereo vision is an essential need for many computer vision applications, such as On Road stereo vision system. In this paper, a fast and accurate system for On-Road stereo vision application is presented. In order to achieve this purpose, first, an algorithm is presented that is optimized for hardware implementation and On-Road application, then an appropriate hardware architecture for this algorithm is proposed. The approach uses gradient and Census transform as initial cost function, then cost is aggregate in cross-based supported reign. LR-check and disparity refinement is also utilized to improve final disparity. The proposed design is a standalone stereo vision system where all steps of algorithm is implemented on a hardware platform. Overall system is implemented on FPGA platform and it is tested on KITTI Database. The proposed system is also tested on Middlebury database without any changes in parameters. Experimental results show that the proposed system has high accuracy in KITTI and Middlebury database. In term of hardware resource, the system occupy %%66 of XC6VLX240T FPGA device for 1920 x 1080 image with 96 disparity levels that operated at 53.5 Fps.

关键词： FPGA Stereo vision On-road image Obstacle Hardware architecture

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Exploration platform of embedded SIMD architecture for autonomous retinas

Exploration platform of embedded SIMD architecture for auton...

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2010 conference on design and architectures for signal and image processing, dasip2010

作者： Chevobbe, Stéphane Pajaniradja, Suresh Letellier, Laurent CEA LIST Embedded Computing Laboratory Gif-sur-Yvette F-91191 France

ISBN: (纸本)9781424487356

An integrated smart camera is a single chip composed of a sensor tightly coupled with one or more processing elements. The image processing applications that are mapped on such systems can require processing power in the range of supercomputer. To face the increasing application needs we propose in this paper a SIMD based processor optimized for the low and intermediate level of image processing. The architecture is composed of several SIMD cluster. Each cluster includes a configurable number of 2-Way PE (processing Element) ranging from 32 to 256 running at 200 MHz. These cluster configurations provide between 12 to 102 GOPS. © 2010 IEEE.

关键词： image processing

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Exploring the Concurrent Execution of HEVC Intra Encoding Algorithms for Heterogeneous Multi Core architectures

Exploring the Concurrent Execution of HEVC Intra Encoding Al...

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conference on design and architectures for signal & image processing

作者： Brandenburg, Jens Stabernack, Benno Heinrich Hertz Inst Nachrichtentech Berlin GmbH Fraunhofer Inst Telecommun Video Coding & Analyt Dept Embedded Syst Grp Einsteinufer 37 D-10587 Berlin Germany

ISBN: (纸本)9791092279115

By introducing novel algorithms in the emerging high efficiency video coding (HEVC) standard average bit-rate savings of 23% have been achieved in comparison to the H.264/AVC high profile reference encoder for the all intra configuration at the cost of an additional complexity increase. This high algorithmic complexity requires the development and integration of innovative approaches, like different parallelization strategies, heterogeneous designs and/or algorithmic optimizations, resulting in a complex design space. Early design verifications as well as performance evaluations are crucial to realize successful solutions, which meet the functional and non-functional constrains respectively. In this paper we propose a SystemC based heterogeneous multi-core model of an HEVC intra encoder, which is used to explore different design aspects and alternatives. Due to its cycle accurate nature the model is well suited to facilitate various performance evaluations and to drive HW/SW co-optimizations of the explored system, as we will discuss in this paper.

关键词： Algorithm design and analysis Encoding Estimation Optimization Prediction algorithms Standards Transforms

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design and analysis of an FPGA based encoder SoC for locally stationary image source

Design and analysis of an FPGA based encoder SoC for locally...

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2013 7th conference on design and architectures for signal and image processing, dasip 2013

作者： Bai, Yuhui Ahmed, Syed-Zahid Granado, Bertrand ETIS - ENSEA - Université Cergy Pontoise - CNRS Cergy France LIP6 - Université Pierre et Marie Curie - CNRS Paris France

ISBN: (纸本)9791092279016

Hierarchical Enumerative Coding (HENUC) is a lossless compression algorithm used in a wavelet based image encoder. By manipulating the wavelet coefficients into locally stationary sequences, HENUC is demonstrated to provide good compression efficiency according to our experimental results. We extended our previous work on FPGA encoder SoC, exploiting an innovative on-chip memory access manner in the bit-plane coding using dual port, as well as an address-based data traversal technique during the coding. Performance results are based on the Altera's 40nm Stratix IV EP4SGX230 FPGA, on a DE4 board from Terasic, where the optimized dual port HENUC architecture is implemented in a Nios II processor based system on chip. We present the resource utilization and the execution time evaluations. We show that our implementation at 100MHz can provide around 10X speedup over 2.4GHz Intel Xeon 8-core CPU, which is about twice as faster as our previous result.

关键词： System-on-chip

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Exploring Custom Heterogeneous MPSoCs for Real-Time Neural signal Decoding

Exploring Custom Heterogeneous MPSoCs for Real-Time Neural S...

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conference on design and architectures for signal & image processing

作者： Meloni, Paolo Tuveri, Giuseppe Pani, Danilo Raffo, Luigi Palumbo, Francesca Univ Cagliari Dipartimento Ingn Elettr & Elettron I-09123 Cagliari Italy Univ Sassari PolComIng Grp Ingn Informaz I-07100 Sassari Italy

ISBN: (纸本)9791092279115

The design of embedded systems for neuroprosthetic applications represents an important challenge to be faced in electronic bioengineering. One of the key research problems is decoding the information encoded in neural signals to extract the patient's motion intention. How to implement a highly-portable and reliable integrated solution is still an open issue. In this paper, we investigate the possibility of adopting the MPSoC paradigm in this application domain, presenting a design space exploration that evaluates different custom MPSoC embedded architectures, implementing an on-line neural signal decoding algorithm. The evaluated design points feature different mappings of parallel software tasks onto customized ASIP processing cores. Experimental results, obtained by FPGA-based prototyping, assess the performance and hardware-related costs of the considered configurations. The clock frequency needed to respect real-time constraints was reduced to 22 MHz, making a step further towards the exploitation of custom heterogeneous MPSoCs for ultra-low power biomedical signal processing.

关键词： Algorithm design and analysis Computer architecture Decoding Noise reduction Program processors Real-Time systems Sorting

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Smart sensor architectures for embedded biosignal analysis

Smart sensor architectures for embedded biosignal analysis

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2013 7th conference on design and architectures for signal and image processing, dasip 2013

作者： Pfundt, Benjamin Reichenbach, Marc Eskofier, Björn Fey, Dietmar Department Computer Science Computer Architecture Friedrich-Alexander-University Erlangen-Nuremberg Germany Department Computer Science Pattern Recognition Lab Friedrich-Alexander-University Erlangen-Nuremberg Germany

ISBN: (纸本)9791092279016

In many sports and medical applications small and wearable sensors are used that capture motion and physiological signals. Yet, commonly such sensor are only capable of acquiring raw data, which is afterwards transmitted to a smartphone or other mobile computing device where processing and classification is carried out. This results in limited usability because another device has to be worn. Moreover, high power consumption due to continuous transmission is a main disadvantage. Therefore, we propose a smart sensor approach that can alleviate these problems by carrying out the processing on the sensor itself. To house the processing schemes in the sensor node we developed a new computer architecture utilizing an FPGA and an ASIC. To show the benefits of the in-sensor processing, we chose two representative biosensor applications: a movement and fall detection system for the elderly and a swimming style recognition system for professional athletes. Compared to conventional approaches the same classification rate can be achieved while saving space, power, weight and setup costs.

关键词： Field programmable gate arrays (FPGA)

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Hyperspectral image classification using a parallel implementation of the linear SVM on a Massively Parallel Processor Array (MPPA) platform

Hyperspectral image classification using a parallel implemen...

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conference on design and architectures for signal and image processing (dasip)

作者： Madronal, D. Lazcano, R. Fabelo, H. Ortega, S. Callico, G. M. Juarez, E. Sanz, C. Tech Univ Madrid UPM Ctr Software Technol & Multimedia Syst CITSEM Madrid Spain ULPGC Res Inst Appl Microelect IUMA Las Palmas Gran Canaria Spain

ISBN: (纸本)9791092279153

In this paper, a study of the parallel exploitation of a Support Vector Machine (SVM) classifier with a linear kernel running on a Massively Parallel Processor Array platform is exposed. This system joins 256 cores working in parallel and grouped in 16 different clusters. The main objective of the research has been to develop an optimal implementation of the SVM classifier on a MPPA platform whilst the architectural bottlenecks of the hyperspectral image classifier are analyzed. Experimenting with medical images, the parallelization of the SVM classification has been conducted using three strategies: i) single- and multi-core processing, ii) single- and multi-cluster analysis and iii) single- and double-buffer execution. As a result, an average core processing speedup of 11.8 has been achieved when parallelizing the SVM classification process in a single cluster. On the contrary, since data communication accounts for 34.7% of the total execution time in the sequential case, the total speedup is upper-bounded to 2.9. Using a double-buffer methodology, a total speedup of 2.84 has been achieved on a single cluster. At last, the feasibility of a portable version of a linear SVM has been demonstrated.

关键词： Support Vector Machine Hyperspectral Imaging Massively Parallel processing Real-time processing Energy consumption awareness

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