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SVM-based real-time hyperspectral image classifier on a manycore architecture

JOURNAL OF SYSTEMS ARCHITECTURE 2017年 80卷 30-40页

作者： Madronal, D. Lazcano, R. Salvador, R. Fabelo, H. Ortega, S. Callico, G. M. Juarez, E. Sanz, C. Univ Politecn Madrid Ctr Software Technol & Multimedia Syst CITSEM Madrid Spain ULPGC Res Inst Appl Microelect IUMA Las Palmas Gran Canaria Spain

This paper presents a study of the design space of a Support Vector Machine (SVM) classifier with a linear kernel running on a manycore MPPA (Massively Parallel Processor Array) platform. This architecture gathers 256 cores distributed in 16 clusters working in parallel. This study aims at implementing a real-time hyperspectral SVM classifier, where real-time is defined as the time required to capture a hyperspectral image. To do so, two aspects of the SVM classifier have been analyzed: the classification algorithm and the system parallelization. On the one hand, concerning the classification algorithm, first, the classification model has been optimized to fit into the MPPA structure and, secondly, a probability estimation stage has been included to refine the classification results. On the other hand, the system parallelization has been divided into two levels: first, the parallelism of the classification has been exploited taking advantage of the pixel-wise classification methodology supported by the SVM algorithm and, secondly, a double-buffer communication procedure has been implemented to parallelize the image transmission and the cluster classification stages. Experimenting with medical images, an average speedup of 9 has been obtained using a single-cluster and double-buffer implementation with 16 cores working in parallel. As a result, a system whose processing time linearly grows with the number of pixels composing the scene has been implemented. Specifically, only 3 mu s are required to process each pixel within the captured scene independently from the spatial resolution of the image. (C) 2017 Elsevier B.V. All rights reserved.

关键词： Support Vector Machine Hyperspectral imaging Massively parallel processing Real-time processing Energy consumption awareness Embedded system

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An experimental toolchain based on high-level dataflow models of computation for heterogeneous MPSoC

An experimental toolchain based on high-level dataflow model...

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6th Annual conference on design and architectures for signal and image processing, dasip 2012

作者： Heulot, J. Desnos, K. Nezan, J.-F. Pelcat, M. Raulet, M. Yviquel, H. Lagalaye, P.-L. Le Lann, J.-C. INSA IETR UMR 6164 UEB 20 av. Buttes de Coësmes 35708 Rennes France IRISA Univ. Rennes 1 6 rue de Kerampont 22300 Lannion France Modaë Technologies 16 Rue Isaac Le Chapelier 35000 Rennes France Labsticc-ENSTA Bretagne France

A chain of three state-of-the-art tools is demonstrated to generate efficient code for Multi-Processors System-on-Chips (MPSoCs) from a high-level dataflow language. The experimental platform is based on a 5-core Texa... 详细信息

ISBN: (纸本)9782953998726

关键词： image processing

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design space exploration strategies for FPGA implementation of signal processing systems using CAL dataflow program

Design space exploration strategies for FPGA implementation ...

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6th Annual conference on design and architectures for signal and image processing, dasip 2012

作者： Rahman, Ab Al-Hadi Ab Thavot, Richard Brunet, Simone Casale Bezati, Endri Mattavelli, Marco SCI-STI-MM École Polytechnique Fédérale de Lausanne Station 11 CH-1015 Lausanne Switzerland

ISBN: (纸本)9782953998726

This paper presents some strategies for design space exploration of FPGA-based signal processing systems that are specified using the CAL dataflow language. The actor-oriented, high-level of abstraction provided by CAL allows flexible exploration and consequently results in a wide range of feasible design implementations. We have applied and extended the existing techniques for refactoring and pipelining actors and actions by means of critical path analysis, and introduced some new buffering techniques based on heuristics. The combinations of these techniques have been applied on the CAL specification of the MPEG-4 video decoder, and synthesized to HDL for evaluation in the design implementation space. Results show that using our configuration for the exploration of 48 design points, a throughput range of roughly 8× has been achieved, for slice, block RAM, frequency, and latency range of 1.3×, 2.5×, 2.5×, and 2.9× respectively. © 2012 ECSI.

关键词： Field programmable gate arrays (FPGA)

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A coarse-grain reconfigurable hardware architecture for RVC-CAL-based design

A coarse-grain reconfigurable hardware architecture for RVC-...

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2010 conference on design and architectures for signal and image processing, dasip2010

作者： Beaumin, Cecile Sentieys, Olivier Casseau, Emmanuel Carer, Arnaud IRISA INRIA University of Rennes 1 6 rue de Kerampont F-22300 Lannion France

ISBN: (纸本)9781424487356

MPEG Reconfigurable Video Coding project aims at providing more flexible and easier solutions to specify video coders and decoders. Many contributions are devoted to the RVCCAL language, the standard description language. There are also contributions about the general framework of this new model of video coding, and many CAL descriptions for video algorithms. However, RVC compliant implementations have been only studied next to code generation which does not take advantage of major characteristics of CAL networks as they are dataflow graphs. Consequently, there are no dedicated architectures that are inherently bound to the CAL language. The objective of this article is to present preliminary work about the design of a co-processor based architecture. The co-processor is a reconfigurable architecture that uses CAL network features and proposes a dynamic memory allocation system, which improves the communication between the processes that are implemented, and enables to allocate minimum memory. © 2010 IEEE.

关键词： Reconfigurable hardware

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High level design space exploration of RVC codec specifications for multi-core heterogeneous platforms

High level design space exploration of RVC codec specificati...

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conference on design and architectures for signal and image processing

作者： Lucarz, Christophe Roquier, Ghislain Mattavelli, Marco Ecole Polytechnique Fédérale de Lausanne CH-1015 Lausanne Switzerland

ISBN: (纸本)9781424487356

Nowadays, the design flow of complex signal processing embedded systems starts with a specification of the application by means of a large and sequential program (usually in C/C++). As we are entering in the multicore era, sequential programs are no longer the most appropriate way to specify algorithms targeted to run on several processing units. The new ISO/MPEG Reconfigurable Video Coding (RVC) standard is proposing a new paradigm for specifying and designing complex signal processing systems. The RVC standard enables specifying new codecs by assembling blocks, or so called Functional Units (FUs) from a standard Video Tool Library (VTL). Flexibility, reusability, and modularity are the key features of RVC. This new way of specifying algorithms clearly simplifies the task of designing future video coding applications by allowing software and hardware reuse across multiple video coding standards. Specifications are provided in the form of an actor and dataflow-based language called CAL. Although the RVC standard does not imply any specific implementation design flow, it is an appropriate starting point for targeting multiple processing units platforms. This paper describes a new model-driven design flow which considers both algorithm and architecture to map RVC codec specifications onto heterogeneous and multi-core systems. © 2010 IEEE.

关键词： Multicore programming

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New 3D-integrated burst image sensor architectures with in-situ A/D conversion

New 3D-integrated burst image sensor architectures with in-s...

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2013 7th conference on design and architectures for signal and image processing, dasip 2013

作者： Bonnard, R. Guellec, F. Segura, J. Dupret, A. Uhring, W. DACLE-L3I CEA-Léti Grenoble France ICube/ESSP/SMH Université de Strasbourg CNRS Strasbourg France

ISBN: (纸本)9791092279016

It is well known that 3D integration technology brings a lot to image sensors in term of fill-factor and in-situ processing. As 3D stacking allows massively parallel processing, it looks like an effective way to store the image close to the pixel in burst image sensor. This paper discusses two new 3D stacked architectures for burst high speed imaging with in-situ A/D conversion, one with analog memories, the other based on digital storage. We propose appraisals of frame-rate, memory depth and power consumption for both architectures. Thanks to this assessment, analog storage architecture appears as a good way to reach unmatched speed performances (>10Terapixel/s) while digital storage architecture seems an interesting solution to reach high memory depth (>200 frames). Moreover, this study identifies a very high power consumption of the digital and analog storage architectures during the image capture.

关键词： image sensors

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Evaluation of analog and digital signal processing on PSoC architecture with DCT as use case

Evaluation of analog and digital signal processing on PSoC a...

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conference on design and architectures for signal & image processing

作者： Werner, Stephan Stiehle, Bernhard Becker, Juergen Karlsruhe Inst Technol Inst Informat Proc Technol ITIV Karlsruhe Germany

ISBN: (纸本)9791092279115

One trend for signal processing hardware is the increasing integration of different functionalities in one mixed-signal chip. But the additional integration of analog components on one chip with digital components and a micro-processor like in the Programmable System on Chip (PSoC) from Cypress is accompanied with the extension of the design space and the need to explore it by evaluating different implementations with the same functionality to find a good trade-off between analog and digital signal processing. This paper evaluates different implementations of the discrete cosine transform (DCT) with different analog-digital partitioning. Therefore the DCT is integrated as software controlled analog circuit based on the switched capacitors and operational amplifiers available in the analog subsystem of the PSoC architecture. The presented analog DCT implementation scales linear and the number of simultaneously computable spectral signal components is only limited by the available on-chip resources on the currently used PSoC5LP. To evaluate the analog implementation, the DCT is also implemented as software executed on the ARM Cortex-M3 integrated in the PSoC5LP. The comparison of both solutions shows that the analog hardware available on the PSoC architecture can be used to directly process analog sensor signals with only minor additional off-chip components with a CPU load of about 8% caused by the software controlling the analog subsystem.

关键词： PSoC DCT discrete cosine transform analog design switched capacitors analog-digital design space exploration mixed signal processing

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Task placement for dynamic and partial reconfigurable architecture

Task placement for dynamic and partial reconfigurable archit...

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2010 conference on design and architectures for signal and image processing, dasip2010

作者： Eiche, Antoine Chillet, Daniel Pillement, Sebastien Sentieys, Olivier University of Rennes I IRISA 6 rue de Kerampont 22302 Lannion France

ISBN: (纸本)9781424487356

Managing tasks and resources of reconfigurable system-on-chip is a complex problem which needs specific operating system (OS) functionalities. One of the most important is the task placement which must be done on-line when the application requires flexibility. To ensure an efficient task placement within the reconfigurable resource, OS services must consider the heterogeneity of the reconfigurable resource. While most publications model the reconfigurable resource as homogeneous area, modern reconfigurable circuits are clearly heterogeneous, i.e. there are based on rectangular grid containing logic blocks but also other blocks such as memories, digital signal processing blocks or hard processor cores. In this paper, we tackle the problem of task placement within a reconfigurable resource and we consider a heterogeneous reconfigurable area. Our solution is based on a neural network structure specifically designed to optimize the task placement problem. Our proposition is based on the knowledge of task instantiations within the reconfigurable resource. Compared with other methods, our proposal provides better results in terms of task rejection. © 2010 IEEE.

关键词： Reconfigurable architectures

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A prototype of an adaptive computer vision algorithm on MPSoC architecture

A prototype of an adaptive computer vision algorithm on MPSo...

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2013 7th conference on design and architectures for signal and image processing, dasip 2013

作者： Sousa, Éricles Rodrigues Tanase, Alexandru Hannig, Frank Teich, Jürgen Hardware/Software Co-Design Department of Computer Science University of Erlangen-Nuremberg Germany

ISBN: (纸本)9791092279016

Continuous software and hardware innovations impose on the one hand a high degree of flexibility from an algorithm and on the other hand it requires that a given processing architecture has the capability to adapt to changing computation patterns at run-time. In this work, we demonstrate how a computer vision application can adapt itself at runtime in order to satisfy different requirements of quality and throughput. For that, we consider an implementation of the Harris Corner Detector on an MPSoC (Multi-Processor System-on-Chip) architecture composed of a quad-core RISC processor and one accelerator based on a programmable massively parallel processor array.

关键词： System-on-chip

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Hardware/software co-design of H.264/AVC encoders for multi-core embedded systems

Hardware/software co-design of H.264/AVC encoders for multi-...

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2010 conference on design and architectures for signal and image processing, dasip2010

作者： Dias, Tiago Roma, Nuno Sousa, Leonel INESC-ID Lisbon ISEL-PI Lisbon IST-TU Lisbon Rua Alves Redol 9 1000-029 Lisbon Portugal

ISBN: (纸本)9781424487356

This paper presents a multi-core H.264/AVC encoder suitable for implementations in small and medium complexity embedded systems. The proposed structure results from an efficient hardware/software co-design methodology, where the encoder software application is highly optimized and structured in a very modular and efficient manner, so as to allow its most complex and time consuming operations to be offloaded to dedicated hardware accelerators. The considered methodology adopts a simple and efficient core interconnection mechanism to easily allow the inclusion and the removal of such optimized processing cores. Experimental results obtained with the implementation in a Virtex4 FPGA of an H.264/AVC encoder using an ASIP IP core as a ME hardware accelerator have proven the advantages of this methodology. For the considered system, speedup factors greater than 15 were obtained with a very modest increase of the involved hardware resources. © 2010 IEEE.

关键词： Embedded systems

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