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检索条件"任意字段=2017 Conference on Design and Architectures for Signal and Image Processing, DASIP 2017"

共 891 条记录，以下是131-140 订阅

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Hardware code generation from dataflow programs

Hardware code generation from dataflow programs

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2010 conference on design and architectures for signal and image processing, dasip2010

作者： Siret, Nicolas Wipliez, Matthieu Nezan, Jean-François Rhatay, Aimad Lead Tech. Design F-35700 Rennes France IETR INSA Rennes F-35043 Rennes France

ISBN: (纸本)9781424487356

The elaboration of new systems on embedded targets is becoming more and more complex. In particular, multimedia devices are now implemented using mixed hardware and software architecture, which improve the computational power but also increase the design complexity and the time to market. New design flows have been developed to help designers in the development of complex architecture. These design flows are often based on the use of languages with a higher level of abstraction. RVC-CAL is a dataflow programming language which provides the good features in this context. An RVC-CAL dataflow program can be compiled to various target software languages (e.g. C, Java, LLVM) with the Open RVC-CAL Compiler (Orcc). In this paper, we will present a new hardware code generator that generates a high-quality portable VHDL code with hierarchical architecture from a RVC-CAL dataflow program in a matter of seconds. The paper explains the underlying principles of the hardware code generator, and presents the results obtained from an Inverse DCT described as an RVC-CAL dataflow program. © 2010 IEEE.

关键词： C (programming language)

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Proceedings of 2021 Workshop on design and architectures for signal and image processing, dasip 2021

Proceedings of 2021 Workshop on Design and Architectures for...

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14th Workshop on design and architectures for signal and image processing, dasip 2021, held jointly with the 16th HiPEAC conference

ISBN: (纸本)9781450389013

The proceedings contain 9 papers. The topics discussed include: architecture of a low latency H.264/AVC video codec for robust ML based image classification;automotive perception system evaluation with reference data obtained by a UAV;convolutional fully-connected capsule network (CFC-CapsNet);DExIE – an IoT-class hardware monitor for real-time fine-grained control-flow integrity;GEGELATI: lightweight artificial intelligence through generic and evolvable tangled program graphs;hardware-software implementation of the PointPillars network for 3D object detection in point clouds;low-power sign-magnitude FFT design for FMCW radar signal processing;multiple transform selection concept modeling and implementation using interface based SDF graphs;and on cache limits for dataflow applications and related efficient memory management strategies.

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design and hardware implementation of a low-complexity multiuser vector precoder

Design and hardware implementation of a low-complexity multi...

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2010 conference on design and architectures for signal and image processing, dasip2010

作者： Barrenechea, Maitane Barbero, Luis Mendicute, Mikel Thompson, John University of Mondragón Department of Electronics and Computer Science Mondragón Spain Queen's University Belfast Institute of Electronics Communications and Information Technology Belfast United Kingdom University of Edinburgh Institute for Digital Communications Edinburgh United Kingdom

ISBN: (纸本)9781424487356

In the multiuser MIMO broadcast channel, the use of precoding techniques is required in order to detect the signal at the users' terminals without any cooperation between them. This contribution presents the design and hardware implementation of a high-capacity precoder based on vector perturbation. The most challenging part of the vector precoding (VP) scheme, that is, the search for the perturbing signal in an infinite lattice, has been completed by the reduced-complexity albeit high-performance Fixed Sphere Encoder (FSE) algorithm. The most remarkable feature of the FSE is its fixed complexity, which makes it highly suitable for hardware implementation on field-programmable gate arrays (FPGA), where the parallelization and pipelining of resources can be applied to enhance the system throughput. An optimized reduced-complexity implementation is proposed, which achieves high performance with a reduced hardware resource usage. © 2010 IEEE.

关键词： Field programmable gate arrays (FPGA)

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FPGA-based rectification of stereo images

FPGA-based rectification of stereo images

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2010 conference on design and architectures for signal and image processing, dasip2010

作者： Rodrigues, João G.P. Ferreiray, João Canas INESC Porto Faculdade de Engenharia Universidade do Porto Portugal IT - Instituto de Telecomunicações Portugal

ISBN: (纸本)9781424487356

In order to obtain depth information about a scene in computer vision, one needs to process pairs of stereo images. The calculation of dense depth maps in real-time is computationally challenging as it requires searching for matches between objects in both images. The task is significantly simplified if the images are rectified, a process which horizontally aligns the objects in both images. The process of stereo images rectification has several steps with different computational requirements. The steps include 2D searches for high fidelity matches, precise matrix calculations, and fast pixel coordinate transformations and interpolations. In this project, the complete process is effectively implemented in a Spartan-3 FPGA, taking advantage of a MicroBlaze soft core for slow but precise calculations, and of fast dedicated hardware support for achieving the real-time requirements. The implemented system successfully performs real-time rectification on the images from two video cameras, with a resolution of 640×480 pixels and a frame rate of 25 fps, and is easily configured for videos with higher resolutions. The experimental results show very good quality, with rectified images having a maximum vertical disparity of two pixels, thereby showing that stereo image rectification can be efficiently achieved in an low-resource FPGA (with 64KB for program instructions and data). © 2010 IEEE.

关键词： Stereo image processing

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Architecture and programming model support for efficient heterogeneous computing on tigthly-coupled shared-memory clusters

Architecture and programming model support for efficient het...

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2013 7th conference on design and architectures for signal and image processing, dasip 2013

作者： Burgio, Paolo Marongiu, Andrea Danilo, Robin Coussy, Philippe Benini, Luca LabSTICC Université de Bretagne-Sud Lorient France ERC MultiTherman Lab DIE Università Degli Studi di Bologna Italy

ISBN: (纸本)9791092279016

Modern computer vision and image processing embedded systems exploit hardware acceleration inside scalable parallel architectures, such as tightly-coupled clusters, to achieve stringent performance and energy efficiency targets. Architectural heterogeneity typically makes software development cumbersome, thus shared memory processor-to-accelerator communication is typically preferred to simplify code offloading to HW IPs for critical computational kernels. However, tightly coupling a large number of accelerators and processors in a shared memory cluster is a challenging task, since the complexity of the resulting system quickly becomes too large. We tackle these issues by proposing a template of heterogeneous shared memory cluster which scales to a large number of accelerators, achieving up to 40% better performance/area/watt than simply designing larger main interconnects to accommodate several HW IPs. In addition, following a trend towards standardization of acceleration capabilities of future embedded systems, we develop a programming model which simplifies application development for heterogeneous clusters.

关键词： Parallel architectures

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A coarse-grained reconfigurable wavelet denoiser exploiting the multi-dataflow composer tool

A coarse-grained reconfigurable wavelet denoiser exploiting ...

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2013 7th conference on design and architectures for signal and image processing, dasip 2013

作者： Carta, Nicola Sau, Carlo Palumbo, Francesca Pani, Danilo Raffo, Luigi DIEE - Dept. of Electrical and Electronic Engineering University of Cagliari P.zza D'Armi 09123 Cagliari Italy

ISBN: (纸本)9791092279016

In the last few years, efficient resource management turned out to be one of the major challenges for hardware designers. Strategies of reusability through reconfiguration have demonstrated interesting potentials to address it, providing also power and area minimization. The Multi-Dataflow Composer (MDC) tool has been presented to the scientific community to automatically build-up runtime coarse-grained reconfigurable platforms. Originally conceived in the field of Reconfigurable Video Coding (RVC), the MDC allows achieving attractive results also for hardware designers operating in different application fields. In this work, we intend to demonstrate the potential orthogonality of the MDC approach with respect to the RVC domain. A runtime reconfigurable wavelet denoiser, targeted for biomedical applications, has been developed and prototyped onto an FPGA Development Board Spartan 3E 1600. Impressive results in terms of resource minimization have been achieved with respect to more traditional solutions.

关键词： Video signal processing

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16th International Workshop on design and architectures for signal and image processing, dasip 2023

16th International Workshop on Design and Architectures for ...

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16th International Workshop on design and architectures for signal and image processing, dasip 2023

ISBN: (纸本)9783031299698

The proceedings contain 9 papers. The special focus in this conference is on design and architectures for signal and image processing. The topics include: Brain Blood Vessel Segmentation in Hyperspectral images Through Linear Operators;Neural Network Predictor for Fast Channel Change on DVB Set-Top-Boxes;AINoC: New Interconnect for Future Deep Neural Network Accelerators;Real-Time FPGA Implementation of the Semi-global Matching Stereo Vision Algorithm for a 4K/UHD Video Stream;TaPaFuzz - An FPGA-Accelerated Framework for RISC-V IoT Graybox Fuzzing;Adaptive Inference for FPGA-Based 5G Automatic Modulation Classification;High-Level Online Power Monitoring of FPGA IP Based on Machine Learning.

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17th International Workshop on design and Architecture for signal and image processing, dasip 2024

17th International Workshop on Design and Architecture for S...

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17th International Workshop on design and Architecture for signal and image processing, dasip 2024

ISBN: (纸本)9783031628733

The proceedings contain 9 papers. The special focus in this conference is on design and Architecture for signal and image processing. The topics include: sEMG-Based Gesture Recognition with Spiking Neural Networks on Low-Power FPGA;A Highly Configurable Platform for Advanced PPG Analysis;preface;Standalone Nested Loop Acceleration on CGRAs for signal processing Applications;optimising Graph Representation for Hardware Implementation of Graph Convolutional Networks for Event-Based Vision;Improving the Energy Efficiency of CNN Inference on FPGA Using Partial Reconfiguration;scratchy: A Class of Adaptable architectures with Software-Managed Communication for Edge Streaming Applications.

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design of fixed-point embedded systems (DEFIS) French ANR project

Design of fixed-point embedded systems (DEFIS) French ANR pr...

引用

6th Annual conference on design and architectures for signal and image processing, dasip 2012

作者： Menard, D. Rocher, R. Sentieys, O. Simon, N. Didier, L.-S. Hilaire, T. Lopez, B. Goubault, E. Putot, S. Vedrine, F. Najahi, A. Revy, G. Fangain, L. Samoyeau, C. Lemonnier, F. Clienti, C. University of Rennes i IRISA/INRIA 6 rue de kerampont F-22300 Lannion France University Pierre et Marie Curie LIP6 4 place Jussieu F-75005 Paris France CEA LIST Saclay Nano-INNOV Point Courrier no 174 F-91191 Gif sur Yvette France Univ. Perpignan Via Domitia DALI/LIRMM F-66860 Perpignan France InPixal 80 Avenue des Buttes de Cosmes F-35700 Rennes France Thales TRandT Route Departementale F-91120 Palaiseau France

ISBN: (纸本)9782953998726

Embedded applications are usually coming with stringent constraints in term of cost, energy consumption and realtime. Consequently, fixed-point arithmetic is mainstream for their implementation into embedded systems. Hence, the main objective of the french ANR project DEFIS is to provide a complete design flow for fixed-point refinement of complex applications. This tool flow is like the missing link between high-level application specification tools and low-level implementation. © 2012 ECSI.

关键词： Embedded systems

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Low power noise detection circuit utilizing switching activity measurement method

Low power noise detection circuit utilizing switching activi...

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2010 conference on design and architectures for signal and image processing, dasip2010

作者： Razak, Zulhakimi Erdogan, Ahmet Arslan, Tughrul System Level Integration Group School of Engineering University of Edinburgh United Kingdom

ISBN: (纸本)9781424487356

Noise often limits the performance of transmitted signals and degrades signals quality. Moreover, stochastic nature of noise makes it difficult to predict, and hence, is hard to detect. In hardware implementation, the reduction of noise can only be optimized in the baseband where complex and intensive computation is executed using digital signal processors (DSPs). Although analog pre-filtering is applied at receiver front-end to reduce interferences, fractions of noise still exist due to non-ideality of the device. We present a method to detect noise in signal using switching activity measurement (SWAM) of analog-to-digital converter (ADC) output. Simulation results show that switching activity of digital outputs varies with different signal-to-noise ratio (SNR) values where high SNR value leads to low switching activity. A noise detection unit (NDU) is implemented and is synthesized using AMS 0.35μm/3.3V CMOS standard library. The result shows minimum overhead where NDU occupies only 774 equivalent 2-input NAND gates and consumes only 978μW of power. With advantage of small complexity and power usage, NDU is attractive to be used in ADC-based systems and noise prone devices in order to detect noise and leads to further signal improvement. © 2010 IEEE.

关键词： signal to noise ratio

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