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IEEE/ACM 36th International conference on Computer-Aided design (ICCAD)

作者： Reiche, Oliver Oezkan, M. Akif Membarth, Richard Teich, Juergen Hannig, Frank Friedrich Alexander Univ Erlangen Nurnberg FAU Dept Comp Sci Nurnberg Germany Saarland Univ German Res Ctr Artificial Intelligence Saarbrucken Germany

ISBN: (纸本)9781538630938

Domain-Specific Languages (DSLs) provide a highlevel and domain-specific abstraction to describe algorithms within a certain domain concisely. Since a DSL separates the algorithm description from the actual target implementation, it offers a high flexibility among heterogeneous hardware targets, such as CPUs and GPUs. With the recent uprise of promising High-Level Synthesis (HLS) tools, like Vivado HLS and Altera OpenCL, FPGAs are becoming another attractive target architecture. Particularly in the domain of image processing, applications often come with stringent requirements regarding performance, energy efficiency, and power, for which FPGA have been proven to be among the most suitable architectures. In this work, we present the Hipacc framework, a DSL and source-to-source compiler for image processing. We show that domain knowledge can be captured to generate tailored implementations for C-based HLS from a common high-level DSL description targeting FPGAs. Our approach includes FPGA-specific memory architectures for handling point and local operators, as well as several high-level transformations. We evaluate our approach by comparing the resulting hardware accelerators to GPU implementations, generated from exactly the same DSL source code.

关键词： DSL Kernel Field programmable gate arrays image processing Tools Graphics processing units Hardware

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An FPGA softcore based implementation of a bird call recognition system for sensor networks

An FPGA softcore based implementation of a bird call recogni...

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conference on design and architectures for signal and image processing

作者： Hongzhi Liu Neil W. Bergmann School of ITEE University of Queensland Australia

To investigate the on-sensor processing capabilities of FPGAs, this paper presents a bird call recognition system based on linear predictive cepstral coefficients (LPCC) and dynamic time warping (DTW) algorithms for sensor network applications, and compares two different implementations on a Xilinx Spartan-3E FPGA with MicroBlaze soft processor. The experimental results show that compared to the software-only solution, the software / hardware (SW/HW) implementation with hardware coprocessor for DTW yields significant performance improvement by the factor of 13.8 and 33.4 respectively for two example inputs, and achieves about 31.1 times energy efficiency by using only 7.5% more power.

关键词： Field programmable gate arrays Hardware Software Birds Feature extraction Digital signal processing Energy efficiency

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VIDEO ACTION RECOGNITION VIA NEURAL ARCHITECTURE SEARCHING 26

VIDEO ACTION RECOGNITION VIA NEURAL ARCHITECTURE SEARCHING

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26th IEEE International conference on image processing (ICIP)

作者： Peng, Wei Hong, Xiaopeng Zhao, Guoying Univ Oulu Ctr Machine Vision & Signal Anal Oulu Finland Xi An Jiao Tong Univ Xian Peoples R China

ISBN: (纸本)9781538662496

Deep neural networks have achieved great success for video analysis and understanding. However, designing a high-performance neural architecture requires substantial efforts and expertise. In this paper, we make the first attempt to let algorithm automatically design neural networks for video action recognition tasks. Specifically, a spatio-temporal network is developed in a differentiable space modeled by a directed acyclic graph, thus a gradient-based strategy can be performed to search an optimal architecture. Nonetheless, it is computationally expensive, since the computational burden to evaluate each architecture candidate is still heavy. To alleviate this issue, we, for the video input, introduce a temporal segment approach to reduce the computational cost without losing global video information. For the architecture, we explore in an efficient search space by introducing pseudo 3D operators. Experiments show that, our architecture outperforms popular neural architectures, under the training from scratch protocol, on the challenging UCF101 dataset, surprisingly, with only around one percentage of parameters of its manual-design counterparts.

关键词： Automated machine learning neural architecture search video action recognition

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New Pilot Allocation design Schemes for Sparse Channel Estimation in OFDM System 5

New Pilot Allocation Design Schemes for Sparse Channel Estim...

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IEEE International conference on signal and image processing Applications (ICSIPA)

作者： Uwaechia, Anthony Ngozichukwuka Mahyuddin, Nor Muzlifah Univ Sains Malaysia Sch Elect & Elect Engn Nibong Tebal 14300 Malaysia

ISBN: (纸本)9781509055593

In this paper, the problem of the deterministic pilot allocation for sparse channel estimation in Orthogonal Frequency Division Multiplexing (OFDM) system is investigated. This method is based on mutual coherence minimization of the measurement matrix associated with the OFDM system pilot subcarriers. It is known that if the set of pilot pattern is a Cyclic Difference Set (CDS), the mutual coherence of the measurement matrix is minimized. However, CDS in most practical OFDM system is not available. Few research efforts have tackled the problem of pilot allocation by proposing methods that lead to suboptimal solutions in order to ignore the computationally complex exhaustive search method. This contribution, however, proposes two pilot allocation design schemes for the construction of deterministic partial Fourier matrices satisfying the Restricted Isometry Property (RIP) namely, the Generic Random Search (GRS) and Progressive Search (PS) based on bounding the mutual coherence between different columns of the measurement matrix. Simulation results show that the two proposed pilot allocation design schemes are effective and offer a better channel estimation performance in terms of MSE when compared to former pilot allocation design methods.

关键词： OFDM Resource management Coherence Channel estimation Minimization Sparse matrices Algorithm design and analysis

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Demo: SLP-aware word length optimization

Demo: SLP-aware word length optimization

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conference on design and architectures for signal and image processing

作者： Ali Hassan El Moussawi Steven Derrien Avenue Général Leclerc Université de Rennes1 Rennes

ISBN: (纸本)9781509030859

Many embedded processors do not support floating-point arithmetic. But they generally provide support for SIMD as a mean to improve performance for near-zero cost overhead. Achieving good performance when targeting such processors requires the use of fixed-point arithmetic and efficient SIMDization. To reduce applications time-to-market, automatic SIMDization and floating-point conversion methodologies have been proposed. In this paper we show that these two problems are strongly related and should be considered jointly. We briefly present a new SLP-aware floating-point conversion flow.

关键词： Program processors Dynamic range Optimization Quantization (signal) Computational modeling Parallel processing Context

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Novel Full-Automatic Approach for Segmentation of Epiretinal Membrane from 3D OCT images 21

Novel Full-Automatic Approach for Segmentation of Epiretinal...

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conference on signal processing: Algorithms, architectures, Arrangements, and Applications (SPA)

作者： Stankiewicz, Agnieszka Marciniak, Tomasz Dabrowski, Adam Stopa, Marcin Rakowicz, Piotr Marciniak, Elzbieta Poznan Univ Tech Inst Automat & Robot Dept Comp Poznan Poland Poznan Univ Med Sci Chair Ophthalmol & Optometry Dept Ophthalmol Poznan Poland Poznan Univ Med Sci Heliodor Swiecicki Med Hosp Poznan Poland

ISBN: (纸本)9788362065301

The scientific objective of the research presented in this paper was to develop a new OCT-based method for investigation of epiretinal membrane (ERM) pathology in human eyes. We propose a new approach for the automatic assessment of the ERM thickness and the space between the ERM and the retina surface. The experiments were conducted using volumetric data acquired from a set of patients with ERM. OCT cross sections were processed frame-by-frame. The utilized advanced digital imaging algorithms included anisotropic diffusion method for denoising, graph analysis approach for ERM surface segmentation, and region growing and thresholding technique for under-ERM space segmentation. We were able to segment and quantify ERMs in all subjects with good precision. The calculated information is presented in the form of depth maps.

关键词： image segmentation retina optical coherence tomography (OCT) epiretinal membrane

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Session 4: Advanced hardware architectures

Session 4: Advanced hardware architectures

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conference on design and architectures for signal and image processing

作者： Morteza Biglari-Abhari University of Auckland (New-Zealand)

ISBN: (纸本)9781509030859

Using hardware architectures to improve performance and energy efficiency has been a key factor for application-specific optimisations. Latest Field Programmable Gate Arrays (FPGA) can not only be used as a reconfigurable hardware platform, they also provide hard core processors and other hard core IPs on the same chip to implement multiprocessor systems on chip, which can be tuned based on the target applications characteristics. In this session, the first two papers present the challenges and optimisations to use hardware architectures based on FPGA for wireless communication systems. In addition an investigation of the crosstalk effects on the Network on Chip energy consumption, as the main interconnection network in multiprocessor systems on chip, is presented.

关键词： hardware architecture Field programmable gate arrays ARCHITECTURE Computer hardware system-on-chip multiprocessor system on chip Hardware Platform Wireless communication systems Interconnection networks Multiprocessor

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Power-Awarness in Coarse-Grained Reconfigurable Multi-Functional architectures: a Dataflow Based Strategy

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JOURNAL OF signal processing SYSTEMS FOR signal image AND VIDEO TECHNOLOGY 2017年第1期87卷 81-106页

作者： Palumbo, Francesca Fanni, Tiziana Sau, Carlo Meloni, Paolo Univ Sassari POLCOMING Informat Engn Unit Sassari Italy Univ Cagliari DIEE Dept Elect Engn Cagliari Italy

Modern embedded systems, to accommodate different applications or functionalities over the same substrate and provide flexibility at the hardware level, are often resource redundant and, consequently, power hungry. Therefore, dedicated design frameworks are required to implement efficient runtime reconfigurable platforms. Such frameworks, to challenge this scenario, need also to offer application specific support for power management. In this work, we adopt dataflow specifications as a starting point to feature power minimization in coarse-grained reconfigurable embedded systems. The proposed flow is composed of two subsequent steps: 1) the characterization of the optimal topological system specification(s) and 2) the identification of disjointed logic regions. These latter are then used to implement clock and power gating methodologies. The validity of this model-based approach has been proved over the reconfigurable computing core of a multi-functional coprocessor for image processing applications. Results have been assessed targeting both an ASIC 90 nm technology and a 45 nm one.

关键词： Power management Coarse-grained reconfiguration Dataflow Power gating Clock gating MPEG-RVC 90 nm CMOS 45 nm CMOS Common Power Format

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Grafik Processor Accelerated Real Time Software Defined Radio Applications 25

Grafik Processor Accelerated Real Time Software Defined Radi...

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25th signal processing and Communications Applications conference (SIU)

作者： Fisne, Alparslan Ozsoy, Adnan ASELSAN AS REHIS EHGYM Bolumu Ankara Turkey Hacettepe Univ Bilgisayar Bilimleri Muhendisligi Bolumu Ankara Turkey

ISBN: (纸本)9781509064946

This paper presents optimizations for spectrogram matrix and signal detection processes which are used for signal sensing in software defined radio (SDR) applications. In industrial and literature applications, the software defined radio or software based receivers include field programmable gate array (FPGA) and digital signal processors (DSP) units for real time signal processing steps. In this study, it is performed real time signal sensing due to using CPU, providing four times speedup compared to multicore CPU which works at same platform. The other important result of our study is making SDR applications at real-time with mobile a computer instead of complex receiver architectures with high cost.

关键词： SDR GPU spectrum signal detection

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Systemc modelization for fast validation of imager architectures

Systemc modelization for fast validation of imager architect...

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conference on design and architectures for signal and image processing

作者： Yves Blanchard Antoine Dupret Arnaud Peizerat ESYCOM ESIEE Paris Paris-Est University Noisy le Grand France LETI-MINATEC CEA Grenoble France

Development of smart CMOS imagers is a complex design task where the verification of an architecture composed of a matrix of pixels intermixed with analog and digital electronics is playing an important part. New generations of imager using 3D integration will allow even more processing to be done in-situ. Verification has to be done locally for the pixel and globally for the architecture. design exploration and validation problematic has shifted from mostly the analog domain to the validation of a complex SOC with millions of parallel processors, the pixels. In this paper we present a methodology using the SystemC language for the creation of fast models for validation and a first level evaluation of performance of large CMOS imager architectures.

关键词： Computational modeling Object oriented modeling Computer architecture Kernel Integrated circuit modeling Adaptation models Hardware

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