检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

859 篇 会议
25 篇 期刊文献
6 册 图书
1 篇 学位论文

馆藏范围

891 篇 电子文献
1 种 纸本馆藏

日期分布

学科分类号

613 篇 工学
- 397 篇 计算机科学与技术...
- 337 篇 电气工程
- 219 篇 信息与通信工程
- 134 篇 软件工程
- 87 篇 电子科学与技术（可...
- 72 篇 仪器科学与技术
- 41 篇 控制科学与工程
- 36 篇 机械工程
- 28 篇 光学工程
- 15 篇 生物医学工程（可授...
- 12 篇 测绘科学与技术
- 11 篇 动力工程及工程热...
- 7 篇 航空宇航科学与技...
- 7 篇 生物工程
- 6 篇 建筑学
- 6 篇 土木工程
- 5 篇 材料科学与工程（可...
- 5 篇 交通运输工程
230 篇 理学
- 146 篇 物理学
- 56 篇 系统科学
- 38 篇 数学
- 10 篇 统计学（可授理学、...
- 7 篇 化学
- 7 篇 生物学
93 篇 医学
- 88 篇 临床医学
- 8 篇 基础医学(可授医学...
- 5 篇 药学(可授医学、理...
30 篇 管理学
- 23 篇 管理科学与工程(可...
- 10 篇 图书情报与档案管...
5 篇 法学
- 4 篇 社会学
3 篇 艺术学
1 篇 教育学
1 篇 军事学

主题

82 篇 field programmab...
63 篇 image processing
59 篇 signal processin...
56 篇 algorithm design...
54 篇 computer archite...
50 篇 hardware
38 篇 estimation
37 篇 clocks
32 篇 ofdm
31 篇 modulation
30 篇 filtration
29 篇 image reconstruc...
28 篇 cameras
28 篇 digital signal p...
27 篇 optimization
23 篇 kernel
23 篇 fpga
22 篇 deep learning
21 篇 feature extracti...
20 篇 image coding

机构

6 篇 national mobile ...
6 篇 lab of efficient...
4 篇 yildiz tekn univ...
3 篇 effat univ elect...
3 篇 stmicroelectroni...
3 篇 agh univ sci & t...
3 篇 beihang univ sta...
3 篇 department of co...
3 篇 ecole polytechni...
3 篇 ietr insa rennes...
3 篇 singapore univ t...
3 篇 zhejiang univ co...
3 篇 tsinghua univ de...
3 篇 ecole polytechni...
3 篇 lodz univ techno...
2 篇 sutd zju idea pe...
2 篇 edinburgh napier...
2 篇 singapore univ t...
2 篇 univ sassari pol...
2 篇 sony lsi design ...

作者

8 篇 chuan zhang
7 篇 mattavelli marco
6 篇 xiaohu you
5 篇 hannig frank
5 篇 fey dietmar
5 篇 palumbo francesc...
5 篇 stabernack benno
4 篇 tomasz kryjak
4 篇 bilge hasan saki...
4 篇 pelcat maxime
4 篇 jean-françois ne...
4 篇 lacassagne lione...
4 篇 margala martin
4 篇 bilgin gokhan
4 篇 marco mattavelli
4 篇 dominique houzet
4 篇 wang yu
4 篇 gorgon marek
4 篇 paolo meloni
4 篇 raffo luigi

语言

829 篇 英文
42 篇 土耳其文
20 篇 中文

检索条件"任意字段=2017 Conference on Design and Architectures for Signal and Image Processing, DASIP 2017"

共 891 条记录，以下是21-30 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

Model-driven reliability evaluation for MPSoC design

Model-driven reliability evaluation for MPSoC design

引用

2017 conference on design and architectures for signal and image processing, dasip 2017

作者： Nguyen, Tien Thanh Mouraud, Anthony Thevenin, Mathieu Corre, Gwenole Pasquier, Olivier Pillement, Sebastien CEA CTREG DPLOIRE 5 rue de l'Halbrane Bouguenais44340 France CEA Saclay Gif-Sur-Yvette91191 France IETR Ecole Polytechnique Nantes Cedex44306 France

ISBN: (纸本)9781538635346

When designing a Multi-Processor System-on-Chip (MPSoC), a very large range of design alternatives arises from a huge space of possible design options and component choices. Literature proposes numerous design-Space-Exploration (DSE) approaches thats mainly focus on cost optimization. In this paper, we present a DSE approach which focuses on the reliability of the whole design. This approach is based on a meta-model of Multi-Processor System-on-Chips (MPSoCs) integrated the reliability evaluation. We develop a tool that allows designers to describe and optimize their platform based on the proposed meta-model. The obtained results of an MPSoC is presented including the improved overall reliability of the system thanks to the automatic selection of the fault tolerance strategies for each component. © 2017 IEEE.

关键词： Fault tolerance

来源：评论

学校读者我要写书评

暂无评论

Power Efficient Dataflow design for a Heterogeneous Smart Camera Architecture

Power Efficient Dataflow Design for a Heterogeneous Smart Ca...

引用

conference on design and architectures for signal and image processing (dasip)

作者： Bhowmik, Deepayan Garcia, Paulo Wallace, Andrew Stewart, Robert Michaelson, Greg Sheffield Hallam Univ Dept Comp Sheffield S1 1WB S Yorkshire England Heriot Watt Univ Sch Engn & Phys Sci Edinburgh EH14 4AS Midlothian Scotland Heriot Watt Univ Math & Comp Sci Edinburgh EH14 4AS Midlothian Scotland

ISBN: (纸本)9781538635346

Visual attention modelling characterises the scene to segment regions of visual interest and is increasingly being used as a pre-processing step in many computer vision applications including surveillance and security. Smart camera architectures are an emerging technology and a foundation of security and safety frameworks in modern vision systems. In this paper, we present a dataflow design of a visual saliency based camera architecture targeting a heterogeneous CPU+FPGA platform to propose a smart camera network infrastructure. The proposed design flow encompasses image processing algorithm implementation, hardware & software integration and network connectivity through a unified model. By leveraging the properties of the dataflow paradigm, we iteratively refine the algorithm specification into a deployable solution, addressing distinct requirements at each design stage: from algorithm accuracy to hardware-software interactions, real-time execution and power consumption. Our design achieved real-time run time performance and the power consumption of the optimised asynchronous design is reported at only 0.25 Watt. The resource usages on a Xilinx Zynq platform remains significantly low.

关键词： Field programmable gate arrays image processing Hardware Smart cameras Computer architecture Computational modeling

来源：评论

学校读者我要写书评

暂无评论

Demo: MPPA® manycore processor towards future ADAS system solutions High-computing platform for next generation vehicles

Demo: MPPA® manycore processor towards future ADAS system s...

引用

conference on design and architectures for signal and image processing (dasip)

作者： Beaucamps, Pierre-Edouard Blanc, Frederic KALRAY Grenoble France

This document describes a demonstration, proposed at dasip Demo Night session. This demonstration is running on a low-power manycore processor from Kalray, named MPPA (R) and is highlighting capabilities of this new g... 详细信息

ISBN: (纸本)9791092279153

关键词： manycore MPPA (R) processor image processing signal processing low-power standalone ADAS

来源：评论

学校读者我要写书评

暂无评论

LibHSA: One Step Towards Mastering the Era of Heterogeneous Hardware Accelerators using FPGAs

LibHSA: One Step Towards Mastering the Era of Heterogeneous ...

引用

conference on design and architectures for signal and image processing (dasip)

作者： Reichenbach, Marc Holzinger, Philipp Haeublein, Konrad Lieske, Tobias Blinzer, Paul Fey, Dietmar Friedrich Alexander Univ Erlangen Nuremberg Chair Comp Architecture Dept Comp Sci Erlangen Germany AMD Bellevue WA USA

ISBN: (纸本)9781538635346

Various signal and image processing applications require vast acceleration in order to enable real-time processing and meet constraints in power consumption. On FPGAs these applications can be implemented as application-specific circuit. Although IP cores for various applications exist, even interfacing these usually requires experienced knowledge in hardware design. Using FPGAs or other accelerators in a heterogeneous system from a host CPU would simplify the usage of accelerator hardware for a common software developer. Recognizing this, several companies and partners from academia created the HSA Foundation (Heterogeneous System Architecture Foundation) to define a platform specification for heterogeneous system requirements as a macro-architecture for efficient and easy targeting heterogeneous processors from popular high-level languages like C/C++, Python, Java and other domain specific languages. In this paper we present an IP library (LibHSA), that greatly simplifies integration of hardware accelerator functions into existing HSA compliant systems. This allows accelerators to take advantage of the existing HSA programming model, libraries, compilers and toolchains. We will demonstrate the work of LibHSA utilizing a programmable image processor implementation on a Xilinx FPGA. The image processor supports low-level algorithms, e.g. Sobel, Median, Laplace, or Gauss. Our results show a substantial decrease integrating customized hardware accelerators using the LibHSA infrastructure. To our knowledge, our library is the first approach for integrating reconfigurable hardware into an HSA compliant system.

关键词： Heterogeneous System architectures HSA Hardware Accelerator image processing FPGA

来源：评论

学校读者我要写书评

暂无评论

Single-FPGA Complete 3D and 2D Medical Ultrasound imager

Single-FPGA Complete 3D and 2D Medical Ultrasound Imager

引用

conference on design and architectures for signal and image processing (dasip)

作者： Ibrahim, A. Simon, W. Doy, D. Pignat, E. Angiolini, F. Arditi, M. Thiran, J-P. De Micheli, G. Ecole Polytech Fed Lausanne Lausanne Switzerland Univ Hosp Ctr CHUV Dept Radiol Lausanne Switzerland Univ Lausanne UNIL Lausanne Switzerland

ISBN: (纸本)9781538635346

3D ultrasound (US) acquisition acquires volumetric images, thus alleviating a classical US imaging bottleneck that requires a highly-trained sonographer to operate the US probe. However, this opportunity has not been explored in practice, since 3D US machines are only suitable for hospital usage in terms of cost, size and power requirements. In this work we propose the first fully-digital, single-chip 3D US imager on FPGA. The proposed design is a complete processing pipeline that includes pre-processing, image reconstruction, and post-processing. It supports up to 1024 input channels, which matches or exceeds state of the art, in an unprecedented estimated power budget of 6.1 W. The imager exploits a highly scalable architecture which can be either downscaled for 2D imaging, or further upscaled on a larger FPGA. Our platform supports both real-time inputs over an optical cable, or test data feeds sent by a laptop running Matlab and custom tools over an Ethernet connection. Additionally, the design allows HDMI video output on a screen.

关键词： Three-dimensional displays Imaging Probes Two dimensional displays Field programmable gate arrays image reconstruction Transducers

来源：评论

学校读者我要写书评

暂无评论

A Review of World's Fastest Connected Component Labeling Algorithms: Speed and Energy Estimation 8

A Review of World's Fastest Connected Component Labeling Alg...

引用

8th conference on design and architectures for signal and image processing (dasip)

作者： Cabaret, Laurent Lacassagne, Lionel Oudni, Louiza Univ Paris Sud Lab Rech Informat F-91405 Orsay France

ISBN: (纸本)9791092279061

Optimizing connected component labeling is currently a very active research field. The current most effective algorithms although close in their design are based on different memory/computation trade-offs. This paper presents a review of these algorithms and a detailed benchmark on several Intel and ARM embedded processors that allows to focus on their advantages and drawbacks and to highlight how processor architecture impact them.

关键词： connected component algorithms Processor architectures

来源：评论

学校读者我要写书评

暂无评论

Reconfigurable Vision processing System for Player Tracking in Indoor Sports

Reconfigurable Vision Processing System for Player Tracking ...

引用

conference on design and architectures for signal and image processing (dasip)

作者： Ibraheem, Omar W. Irwansyah, Arif Hagemeyer, Jens Porrmann, Mario Rueckert, Ulrich Bielefeld Univ CITEC Cognitron & Sensor Syst Grp Bielefeld Germany

ISBN: (纸本)9781538635346

In recent years, there has been an increasing growth of using vision-based systems for tracking the players in team sports to evaluate and enhance their performance. Vision-based player tracking has high computational demands since it requires processing of a huge amount of video data based on the utilization of multiple cameras with high resolution and high frame rates. In this paper, we present a reconfigurable system to track the players in indoor sports automatically without user interaction. The proposed system can process live video data streams from multiple cameras as well as offline data from recorded video files. FPGA technology is used to accelerate this player tracking system by implementing the video acquisition, video preprocessing, player segmentation, and team identification & player detection modules in hardware, realizing a real-time system. The teams are identified and the players' positions are detected based on the colors of their jerseys. The detection results are sent from the FPGA to the host-PC where the players are tracked. Our results show that the achieved average player detection rate is up to 95.5%. The proposed system can process live video data using two GigE Vision cameras with a resolution of 1392x1040 pixels and 30 fps for each camera. A speed-up of 20 is achieved compared to an OpenCV-based software implementation on a host-PC equipped with a 2.93 GHz Intel i7 CPU.

关键词： Streaming media Cameras Field programmable gate arrays IP networks image color analysis Games Target tracking

来源：评论

学校读者我要写书评

暂无评论

Embedded Fluorescence Lifetime Determination for High Throughput Real-Time Droplet Sorting with Microfluidics

Embedded Fluorescence Lifetime Determination for High Throug...

引用

conference on design and architectures for signal and image processing (dasip)

作者： Lieske, Tobias Uhring, Wilfried Dumas, Norbert Leonard, Jeremie Fey, Dietmar Friedrich Alexander Univ Erlangen Nurnberg FAU Dept Comp Sci Chair Comp Architecture Erlangen Germany Univ Strasbourg ICube Strasbourg France CNRS Paris France Univ Strasbourg IPCMS Strasbourg France

ISBN: (纸本)9781538635346

Time-resolved fluorescence (TRF) analysis is considered to be among the primary research tools in biochemistry and biophysics. One application of this method is the investigation of biomolecular interactions with promising applications for biosensing. For the latter context, time-correlated single photon counting (TCSPC) is the most sensitive, hence preferred implementation of TRF. However, high throughput applications are presently limited by the maximum achievable photon acquisition rate, and even more by the data processing rate. The latter rate is actually limited by the computational complexity to estimate accurately the fluorescence lifetime from TCSPC data. Here we propose a solution that would enable the implementation of TRF detection for fluorescence-activated droplet sorting (FADS), a particularly high throughput, microfluidic-based technology. Most fluorescence lifetime algorithms require a large number of detected photons for an accurate lifetime computation. This paper presents an implementation based on a maximum likelihood estimator (MLE), enabling high precision estimation with a limited number of detected photons, significantly reducing the total measurement time. This speedup rapidly increases the input data rate. As a result, off-the-shelf embedded products cannot handle the data rates produced by current TCSPC units that are used to measure the fluorescence. Therefore, a configurable real-time capable hardware architecture is implemented on a field programmable gate array (FPGA) that can handle the data rates of future TCSPC units, rendering high throughput droplet sorting with microfluidics possible.

关键词： FPGA time-resolved fluorescence fluorescence lifetime microfluidics embedded signal processing

来源：评论

学校读者我要写书评

暂无评论

Demo: Overlay architectures For Heterogeneous FPGA Cluster Management

Demo: Overlay Architectures For Heterogeneous FPGA Cluster M...

引用

conference on design and architectures for signal and image processing (dasip)

作者： Bollengier, Theotime Najem, Mohamad Le Lann, Jean-Christophe Lagadec, Loic B Com Brest France ENSTA Bretagne Lab STICC MOCS Brest France

ISBN: (纸本)9791092279153

Overlays are reconfigurable architectures synthesized on commercial of the shelf (COTS) FPGAs. Overlays bring some advantages such as portability, resources abstraction, fast configuration, and can exhibit features independent from the host FPGA. We designed a fine-grained overlay implementing novel features easing the management of such architectures in a cluster of heterogeneous COTS FPGAs. This demonstration shows the use of this overlay in an FPGA cluster, performing a hardware application live migration between two nodes of a cluster. It also illustrates fault tolerance of the cluster.

关键词： Field programmable gate arrays (FPGA)

来源：评论

学校读者我要写书评

暂无评论

design Flow for Portable Dataflow Programming of Heterogeneous Platforms 12

Design Flow for Portable Dataflow Programming of Heterogeneo...

引用

12th conference on design and architectures for signal and image processing (dasip)

作者： Boutellier, Jani Lunnikivi, Henri Tampere Univ Technol Lab Pervas Comp Tampere Finland

ISBN: (纸本)9781538682371

The processing platforms of contemporary mobile devices are commonly built around System-on-Chip (SoC) solutions that contain general purpose processor cores (GPPs), digital signal processors, accelerator circuits, and possibly a graphics processing unit (GPU) as processing resources. Software design for such SoCs can be very time-consuming, as the various processing resource types (e.g. GPPs and GPUs) conventionally require different languages to be programmed. For example, GPUs are programmed via CUDA or OpenCL, whereas GPPs are commonly programmed in C++. As a consequence, code that has originally been written for one processing resource, cannot necessarily be executed on a different processing resource type. This paper presents a novel design flow that addresses this code portability challenge. On a high level the application is described using a dataflow graph, whereas the detailed functionality of application components is written in Halide, a performance portable language that provides code generation for OpenCL, CUDA, HVX DSP, ARM and x86 targets. The proposed design flow is built around PRUNE, a recent dataflow programming framework. The functionality of the design flow is presented with three case study applications, and the measurements show an average speedup of 9.3x over single-core C code when the proposed design flow is used.

关键词： dataflow programming parallel processing digital signal processing

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共90页 << < 1 2 3 4 5 6 7 8 9 10 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：