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检索条件"任意字段=2017 Conference on Design and Architectures for Signal and Image Processing, DASIP 2017"

共 891 条记录，以下是301-310 订阅

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On Cache Limits for Dataflow Applications and Related Efficient Memory Management Strategies 21

On Cache Limits for Dataflow Applications and Related Effici...

引用

14th Workshop on design and architectures for signal and image processing, dasip 2021, held jointly with the 16th HiPEAC conference

作者： Ghasemi, Alemeh Cataldo, Rodrigo Diguet, Jean-Philippe Martin, Kevin J. M. Université de Bretagne-Sud France

ISBN: (纸本)9781450389013

The dataflow paradigm frees the designer to focus on the functionality of an application, independently from the underlying architecture executing it. While mapping the dataflow computational part to the cores seems obvious, the memory aspects do not match accordingly. Dataflow compilers usually do not consider the presence of caches when generating code. A generally accepted idea is that bigger and multi-level caches improve the performance of applications. Unfortunately, state-of-the-art dataflow compilers may prove the exception to this rule. This paper presents two efficient memory management strategies for dataflow applications through a study on the impact of sharing, size, and the number of levels of caches on them. The results show that bigger is not always better, and the foreseen future of more cores and bigger caches do not guarantee software-free better performance for dataflow applications. We propose two strategies, that can be used concurrently, to address the memory aspects of the dataflow model: copy-on-write and non-temporal memory transfers. Experimental results show that we speed up a computer stereo vision application by 2.1 × and reduce the number of L1 data cache misses by 45% while maintaining the actors' source code and design intact. © 2021 ACM.

关键词： Stereo image processing

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Quality Measurement of Fruits and Vegetables with Near Infrared Camera 25

Quality Measurement of Fruits and Vegetables with Near Infra...

引用

25th signal processing and Communications Applications conference (SIU)

作者： Turker, Didem Sezer, Recep Isik, Sahin Ozkan, Kemal Istanbul Tech Univ Bilgisayar Muhendisligi Istanbul Turkey Eskisehir Osmangazi Univ Bilgisayar Muhendisligi Eskisehir Turkey

ISBN: (纸本)9781509064946

The determination of the quality of some foods with traditional techniques is considered as deceptive and costly. For this reason, more objective and fair methods are preferred for the measurement of food quality. In food industry it is very common to use image processing methods that uses the color, size etc. of foods to measure the quality and to classify them. In this study, it is aimed to measure the quality of food products (vegetables and fruits) with computerized systems as easily and objectively by a near infrared spectroscopy.

关键词： near infrared spectroscopy food quality image processing

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design of a processor optimized for syntax parsing in video decoders

Design of a processor optimized for syntax parsing in video ...

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conference on design and architectures for signal and image processing

作者： Nicolas Siret Jean-François Nezan Aimad Rhatay INSA IETR UMR 6164 European university of Brittany Rennes France Lead Tech Design Rennes France

Heterogeneous platforms aim to offer both performance and flexibility by providing designers processors and programmable logical units on a single platform. Processors implemented on these platforms are usually soft-cores (e.g. Altera NIOS) or ASIC (e.g. ARM Cortex-A8). However, these processors still face limitations in terms of performance compared to full hardware designs in particular for real-time video decoding applications. We present in this paper an innovative approach to improve performance using both a processor optimized for the syntax parsing (an Application-Specific Instruction-set Processor) and a FPGA. The case study has been synthesized on a Xilinx FPGA at a frequency of 100 MHz and we estimate the performance that could be obtained with an ASIC.

关键词： Computer architecture Decoding Registers Hardware Software Syntactics Streaming media

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Development of a method for image-based motion estimation of a VTOL-MAV on FPGA

Development of a method for image-based motion estimation of...

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conference on design and architectures for signal and image processing

作者： N. Frietsch I. Pashkovskiy G. F. Trommer L. Braun M. Birk M. Hubner J. Becker Institute of Systems Optimization (ITE) Karlsruhe Institute of Technology Karlsruhe Germany Institute for Information Processing Technologies (ITIV) Karlsruhe Institute of Technology Karlsruhe Germany

In this paper, the development of the vision based motion estimation for a small-scale VTOL-MAV as well as the implementation on FPGA are investigated. Especially in urban environments the GPS signal quality is disturbed by shading and multipath propagation and an augmentation with another sensor is inevitable. The vision system bases on the analysis of the sparse optical flow that is extracted from images taken by the onboard camera. From the extracted point correspondences projective transformations are estimated with a robust parameter estimation algorithm. As the underlying image processing routines are computationally expensive but can be processed in parallel they have been implemented on FPGA. The different parts of the algorithm as well as the implementation are covered in detail.

关键词： Feature extraction Optical imaging Cameras Field programmable gate arrays Adaptive optics Clocks Equations

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Exploring custom heterogeneous MPSoCs for real-time neural signal decoding

Exploring custom heterogeneous MPSoCs for real-time neural s...

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conference on design and architectures for signal and image processing

作者： Paolo Meloni Giuseppe Tuveri Danilo Pani Luigi Raffo Francesca Palumbo Dipartimento Ingegneria Elettrica ed Elettronica Università degli Studi di Cagliari Cagliari Italy PolComIng - Gruppo Ingegneria dell'Informazione Università degli Studi di Sassari Sassari Italy

The design of embedded systems for neuroprosthetic applications represents an important challenge to be faced in electronic bioengineering. One of the key research problems is decoding the information encoded in neural signals to extract the patient's motion intention. How to implement a highly-portable and reliable integrated solution is still an open issue. In this paper, we investigate the possibility of adopting the MPSoC paradigm in this application domain, presenting a design space exploration that evaluates different custom MPSoC embedded architectures, implementing an on-line neural signal decoding algorithm. The evaluated design points feature different mappings of parallel software tasks onto customized ASIP processing cores. Experimental results, obtained by FPGA-based prototyping, assess the performance and hardware-related costs of the considered configurations. The clock frequency needed to respect real-time constraints was reduced to 22 MHz, making a step further towards the exploitation of custom heterogeneous MPSoCs for ultra-low power biomedical signal processing.

关键词： Sorting Program processors Decoding Real-time systems Computer architecture Noise reduction Algorithm design and analysis

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Multiplier free filter bank based concept for blocker detection in LTE systems

Multiplier free filter bank based concept for blocker detect...

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conference on design and architectures for signal and image processing

作者： Thomas Schlechter Institute of Networked and Embedded Systems Klagenfurt University Klagenfurt Austria

Power efficiency is an important issue in mobile communication systems. Especially for mobile user equipments, the energy budget, limited by a battery, has to be treated carefully. Despite this fact, quite an amount of energy is wasted in todays user equipments, as analog and digital frontend in communication systems are engineered for extracting the wanted signal from a spectral environment defined in the corresponding communication standards with their extremely tough requirements. In a real receiving process those requirements can typically be considered as dramatically less critical. Capturing the environmental transmission conditions and adapting the receiver architecture to the actual needs allows to save energy during the receiving process. An efficient architecture being able to fulfill this task for a typical Long Term Evolution scenario is desired and introduced in this paper. The development of a suitable filterchain is described and a complexity comparison to Fast Fourier Transformation based methods is given.

关键词： Complexity theory signal resolution Hardware Energy consumption Bandwidth Sensors Energy resolution

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image Enhancement with Outlier Detection 25

Image Enhancement with Outlier Detection

引用

25th signal processing and Communications Applications conference (SIU)

作者： Anagun, Yildiray Adar, Nihat Seke, Erol Eskisehir Osmangazi Univ Bilgisayar Muhendisligi Bolumu ESOGU Meselik Yerleskesi TR-26480 Eskisehir Turkey Eskisehir Osmangazi Univ Elekt & Elekt Muhendisligi Bolumu ESOGU Meselik Yerleskesi TR-26480 Eskisehir Turkey

ISBN: (纸本)9781509064946

In this study, a new method is proposed to achieve a high resolution (HR) image from low resolution (LR) video frames, which include camera motions as well as local motions. The best matching block in the motion estimation is obtained by using the variable size block matching (VSBM) algorithm. Furthermore, before merging the pixels, the outlier pixels were cleaned using statistical outlier detection method. Peak-signal-to-noise ratio (PSNR) and structural similarity index measurement (SSIM) were used to compare the experimental results of the proposed method.

关键词： image enhancement outlier detection variable size block matching

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Tamper Localization of the Medical images Based on Fragile Watermarking 25

Tamper Localization of the Medical Images Based on Fragile W...

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25th signal processing and Communications Applications conference (SIU)

作者： Ustubioglu, Arda Ulutas, Guzin Ustubioglu, Beste Karadeniz Tech Univ Bilgisayar Muhendisligi Trabzon Turkey

ISBN: (纸本)9781509064946

Flexible usage and easy acquisition of image processing software has made "tamper localization in medical images" a popular area. Medical image Watermarking (MIW), which is one of the recommended methods in this area, relies on embedding additional information into the original image. In general, the medical image is separated into two parts called ROI - Region of Interest and RONI - Region of NonInterest. In the proposed method, image is separated into non-overlapping 8x8 blocks and then the BTLV (Block Tamper Localization Vector) of the corresponding block is calculated and embedded to tamper localization on the ROI. Similar works in the literature determined small size in ROI but it can reach up %80 of the image in the proposed method. Experimental results also indicate that proposed method gives higher PSNR for watermarked images and Normalize Correlation (NC) value is also better than the similar works.

关键词： Medical image Watermarking Tamper Localization Discrete Cosine Transform

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Learning Local Receptive Fields and their Weight Sharing Scheme on Graphs 5

Learning Local Receptive Fields and their Weight Sharing Sch...

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5th IEEE Global conference on signal and Information processing (GlobalSIP)

作者： Vialatte, Jean-Charles Gripon, Vincent Coppin, Gilles City Zen Data 55 Rue Charles Nungesser F-29490 Guipavas France IMT Atlantique CNRS Lab STICC Technopole Brest Iroise F-29238 Brest France

ISBN: (纸本)9781509059904

We propose a simple and generic layer formulation that extends the properties of convolutional layers to any domain that can be described by a graph. Namely, we use the support of its adjacency matrix to design learnable weight sharing filters able to exploit the underlying structure of signals in the same fashion as for images. The proposed formulation makes it possible to learn the weights of the filter as well as a scheme that controls how they are shared across the graph. We perform validation experiments with image datasets and show that these filters offer performances comparable with convolutional ones.

关键词： deep learning convolutional neural networks local receptive fields graph signal processing

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Analysis of Vedic Multiplier using Various Adder Topologies 4

Analysis of Vedic Multiplier using Various Adder Topologies

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4th International conference on signal processing and Integrated Networks (SPIN)

作者： Akhter, Shamim Saini, Vikas Saini, Jasmine JIIT Noida ECE Dept Noida India

ISBN: (纸本)9781509027972

Vedic maths based multiplier is a novel and high speed multiplier. Adder is one of the main components used in this technique. Using fast adder will enhance the overall performance of the Vedic multiplier. In this work, comparative analysis is done using different adder architectures in Synopsis design Compiler with different standard cell libraries at 32/28 nm. Various Adder topologies like Ripple Carry Adder (RCA), Carry Select Adder (CSA), Square Root Carry Select Adder (SQRT-CSA), Common Boolean Logic (CBL) and Binary to Excess one Converter (BEC) are used to compare area, delay and power. designing is done for 8-bit, 16-bit, 32-bit and 64-bit Vedic multiplier using the above adders. It is found that 64-bit Vedic multiplier using SQRT-CSA adder is approximately 5% faster than RCA-CSA and BEC, 75% faster than CBL and RCA

关键词： Vedic Multiplier RCA CBL BEC CSA SQRT-CSA design Compiler Power Delay Area

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