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检索条件"任意字段=2017 Conference on Design and Architectures for Signal and Image Processing, DASIP 2017"

共 891 条记录，以下是511-520 订阅

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Asynchronous Interface FIFO design on FPGA for High-throughput NRZ Synchronisation 27

Asynchronous Interface FIFO Design on FPGA for High-throughp...

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27th International conference on Field Programmable Logic and Applications (FPL)

作者： Liu, Gengting Garside, James Furber, Steve Plana, Luis A. Koch, Dirk Univ Manchester Sch Comp Sci Manchester M13 9PL Lancs England

ISBN: (纸本)9789090304281

Networks-on-chip (NoCs) have become a new chip design paradigm as the size of transistors continues to shrink. Globally-asynchronous locally-synchronous (GALS) on-chip networks are proposed for solving issues such as large clock tree distribution and signal delay variations. More interestingly, for the GALS networks using m-of-n delay-insensitive interconnect, the asynchronous interconnect not only can be used for on-chip interconnection, but also provides a simple, direct and power-saving solution for off-chip interconnection. This paper presents an asynchronous interface FIFO design to improve throughput over asynchronous inter-chip links using 2-of-7 Non-Return-to-Zero (NRZ) encoding in an existing many-core system. The proposed design is suitable for implementation on commodity FPGAs without using the limited global clock buffer resources, but involves using the FPGA to implement asynchronous circuits. The interface FIFO is constructed from the transition detectors themselves rather than by employing a separate buffer in the more conventional fashion. The proposed solution has been demonstrated in an existing system and is suitable for adaptation to other asynchronous m-of-n NRZ coding protocols for high-throughput communication.

关键词： Detectors image edge detection Field programmable gate arrays Synchronization Optical signal processing Encoding

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design of Radix-4,16,32 Approx Booth Multiplier Using Error Tolerant Application 6

Design of Radix-4,16,32 Approx Booth Multiplier Using Error ...

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6th International conference on Reliability, Infocom Technologies and Optimization (Trends and Future Directions) (ICRITO)

作者： Jain, Gunjan Jain, Meenal Gupta, Gaurav MITRC Dept Elect & Commun Engn Alwar India

ISBN: (纸本)9781509030125

Approximate computing has a very important contribution in the multimedia world. Approximate computing consists of arithmetic circuits such as adder, multiplier etc. Which are based on the approximate technique or error tolerant application. These arithmetic circuits have high efficiency and better performance, but less accurate. In an electronic world, many applications are used such as signal processing, network signaling, image processing, neural networks where multiplier is used as an arithmetic circuit. In this way, approximate multiplier shows some mean error which is not so important at large. This multiplier makes significant improvements in power, delay, and area at the expense of reducing accuracy. The approximate multiplier is to use less power and area than conventional truncated multiplier, and keep high speed. Its main purpose is to speed up the speed of arithmetic circuits as well as spend low power. A lot of process is being taken to fulfill this objective Like ETM (Error tolerant Multiplier), UDM (Under designed Multiplier), AWTM (Approx Wallace Tree Multiplier), AM (Approx Multiplier). In this paper, the approximate Booth Multiplier has been designed which works on error tolerant multiplication (ETM) technology and provides high performance for the DSP application. This Error Tolerant Application easily restrict on accuracy and achieve various improvement in power consumption and speed accuracy. A new type of approximate multiplier has been designed in this multiplier which can increase the speed by reducing the partial product of the traditional multiplier. According to this paper is to design such a high-speed radix signed approximate booth multiplier which provides significant improvements in power, delay and area at low cost performance in accuracy.

关键词： Approx Wallace Tree Multiplier (AWTM) Digital signal processing(DSP) Error Tolerant Multiplier (ETM) Low power Modified Booth Multiplier Multiplier Radix Truncated

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ACM International conference Proceeding Series

ACM International Conference Proceeding Series

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2nd International conference on Biomedical signal and image processing, ICBIP 2017

ISBN: (纸本)9781450352680

The proceedings contain 17 papers. The topics discussed include: automatic identification of circulating tumor cells in fluorescence microscopy images based on ANN;identification of sudden cardiac arrest (SCA) using modified wavelet transform;design of smart shopping wall using hand gesture and facial image recognition;classification of handwritten Tamil characters in palm leaf manuscripts using SVM based smart zoning strategies;pattern recognition in thought-form images using radon transform and histograms;an interactive technique of fast vertebral segmentation for computed tomography images with bone metastasis;statistical shape model generation using diffeomorphic surface registration;SAM filter based convolution neural network algorithm for leukocyte classification;and multimodal and multispectral imaging for chronic pressure ulcer assessment.

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Research and Implementation for Quadrature Digital Down Converter of Low Intermediate Frequency signal Based on FPGA

Research and Implementation for Quadrature Digital Down Conv...

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International conference on Information Technology and Intelligent Transportation Systems (ITITS)

作者： Kang Jun-min Changan Univ Sch Informat Engn Xian 710064 Peoples R China

ISBN: (纸本)9783319387895;9783319387871

For the receiver of Global Navigation Satellite System, quadrature digital down converter of low intermediate frequency signal can reduce the data rate and improve the real-time processing ability of baseband. But the phase quantization and amplitude quantization of existing methods may introduce new errors which could have a serious impact on the receiver's ultimate accuracy. According to the result of extensive research in the processing method for quadrature digital down converter, optimization the structure of polyphase filter, Integrated planning for the receiver with the unified optimization of RF chip and baseband circuit. design a quadrature digital down converter structure which shared with capture mode and tracking mode, and does not introduce gain error and phase error. Simulation and application test results showed that compared with classic quadrature digital down converters, the design put forward in this pater can avoid data and phase truncation with a simple structure and faster processing speed. Under the same image frequency rejection ratio, its circuit is smaller. Practice has proved that the proposed FPGA structure is very suitable for the BeiDou Navigation Satellite System.

关键词： Satellite navigation BeiDou Navigation Satellite System (BDS) Digital signal processing Quadrature down converter FPGA

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DAMAGE DEVELOPMENT IN SIC_F/SIC COMPOSITES THROUGH MECHANICAL LOADING

DAMAGE DEVELOPMENT IN SIC<sub>F</sub>/SIC COMPOSITES THROUGH...

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ASME Turbo Expo: Turbine Technical conference and Exposition

作者： Bache, Martin R. Jones, J. Paul Quiney, Zak Gale, Louise Swansea Univ Inst Struct Mat Coll Engn Swansea SA1 8EN W Glam Wales Rolls Royce PLC POB 31 Derby DE24 8BJ England

ISBN: (纸本)9780791850916

Sophisticated mechanical characterisation is vital in support of a fundamental understanding of deformation in ceramic matrix composites. On the component scale, "damage tolerant" design and lifing philosophies depend upon laboratory assessments of macro-scale specimens, incorporating typical fibre architectures and matrix under representative stress-strain states. Standard SiCf/SiC processing techniques inherently introduce porosity between the individual reinforcing fibres and between woven fibre bundles. Subsequent mechanical loading (static or cyclic) may initiate cracking from these stress concentrations in addition to fibre/matrix decohesion and delamination. The localised coalescence of such damage ultimately leads to rapid failure. Proven techniques for the monitoring of damage in structural metallics, i.e. optical microscopy, potential drop systems, acoustic emission (AE) and digital image correlation (DIC), have been adapted for the characterisation of CMC's tested at room temperature. As processed SiCf/SiC panels were subjected to detailed X-ray computed tomography (XCT) inspection prior to specimen extraction and subsequent static and cyclic mechanical testing to verify their condition. DIC strain measurements, acoustic emission and resistance monitoring were performed and correlated to monitor the onset of damage during loading, followed by intermittent XCT inspections throughout the course of selected tests.

关键词： image correlation

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design, field testing, and application of a new through-the-bit fullbore microelectrical imaging tool in unconventional reservoirs of North America

Design, field testing, and application of a new through-the-...

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SPE Annual Technical conference and Exhibition 2017

作者： Haddad, E. Wells, P. Fredette, M. Toniolo, J. Mallick, A. Nguyen, H. Bammi, S. Laronga, R.J. Kherroubi, J. He, A. Gelman, A. Jarrot, A. Fratarcangeli, D. Alcorn, T. Tipton, T. Schlumberger China Tapstone Energy United States

Microelectrical imaging is a well-known and highly versatile geological and reservoir characterization technique that produces representative and photorealistic images of the formations intersected by a wellbore to form the basis of a thorough and reliable geological interpretation. These images are used to characterize geological structures, natural fractures, faults and interpret sedimentary features and rock facies. This paper introduces the world's first through-the-bit microelectrical imaging tool, also the world's smallest tool in the genre, at 2-1/8 in diameter and 140 lbs. The new tool provides the lowest-cost, lowest-risk method to obtain high-quality images in lateral wells for applications such as fracture characterization of unconventional reservoirs. We present the electrical and mechanical design innovations that enabled repackaging the performance of the industry-standard microelectrical imaging tool into a 'nano' format tough enough to withstand the rigors of through-the-bit conveyance, often in laterals that exceed two miles' length. The basic physics of the industry-standard are maintained with some obvious changes to the geometry. A simple and elegant twelvearm bowspring design maximizes coverage of the borehole wall, while being robust enough to prevent pads from being ripped off downhole, a well-known fault of existing imaging tools in lateral wells. Inpad front-end signal processing of twelve buttons ensures strong signal-to-noise while demanding further innovation in miniaturization. Notwithstanding its diminutive size, the new tool delivers images of 5mm nominal resolution and 76% circumferential coverage in six inch boreholes drilled with water-base fluids. We discuss implications of the new design for the image data processing chain, as development of significant new and tool-specific processing methods was necessary. For example, the irregularity of tool movement in long laterals, the lack of wireline cable depth measurement during logging

关键词： image enhancement

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Energy-Efficient Synchronous Counter design with Minimum Hardware Overhead 6

Energy-Efficient Synchronous Counter Design with Minimum Har...

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IEEE International conference on Communication and signal processing (ICCSP)

作者： Katreepalli, Raghava Haniotakis, Themistoklis Southern Illinois Univ Carbondale Dept Elect & Comp Engn Carbondale IL 62901 USA

ISBN: (纸本)9781509038008

The Performance of any VLSI circuit depends on its design architecture, which optimizes power and provides high reliability. To design any circuit with low power, power optimization of circuit at different levels is needed. Most of the system level architectures consists of sequential circuits, design of these circuits plays an pivotal role in reducing overall energy of the system. Counters are basic building blocks in many VLSI applications such as timers, memories, ADCs/DACs, frequency dividers etc. It is observed that design of counters has power overhead because of requirement of high power consumption for the clock signal distribution and undesired activity of flip-flops due to presence of clocks. In this paper we propose an energy efficient design of synchronous counters that reduces the power consumption due to clock distribution for different flip-flops and offers high reliability. The proposed counter design is evaluated and anlayzed in terms of energy in a standard 45nm CMOS technology in CADENCE. The proposed counter design has lower energy requirement than existing counter architectures and the energy reduction is more significant for wide-bit counters.

关键词： counter power conumption energy clock power

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Performance Analysis of 1-Bit Full Adder using Different design Techniques 2

Performance Analysis of 1-Bit Full Adder using Different Des...

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2nd IEEE International conference on Recent Trends in Electronics, Information and Communication Technology (RTEICT)

作者： Sreelatha, P. Lakshmi, P. Koti Rao, Rameshwar Osmania Univ UCE ECE Dept Hyderabad Andhra Prades India Osmania Univ Dept ECE UCE Hyderabad Andhra Prades India

ISBN: (纸本)9781509037049

A fast and power-efficient full Adder plays key role in electronics trade especially performing arithmetic operations in microprocessors, digital signal processing (DSP) and image processing. Full Adder is such a significant element which contributes substantially to the total power consumption of the network. In this paper, 1-bit Full Adder has been designed which is then analyzed. The leakage power consumption has been done in the circuit using different technologies such as 120nm and 180nm. The designed circuit has shown a incredible reduction in the consumed power of 97.8% and an increase of 12.7% in consumed area compared to GDI full adder in 120nm foundry. By using DSCH2 and MICROWIND2 tools, the designed 1-bit complete adder are compared in phrases of leakage power consumption and surface area.

关键词： CMOS VLSI Full Adder Power consumption CMOS technology

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2D optical accelerometer using POF array and image detection 25

2D optical accelerometer using POF array and image detection

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25th International conference on Plastic Optical Fibres, POF 2016

作者： Serrão, R. Antunes, P. André, P.S. Department of Electrical and Computer Engineering Instituto Superior Técnico University of Lisboa Lisboa Portugal Instituto de Telecomunicações Physics Department I3N University of Aveiro Aveiro Portugal Department of Electrical and Computer Engineering Instituto de Telecomunicações Instituto Superior Técnico University of Lisboa Lisboa Portugal

ISBN: (纸本)9781854494085

In this work we propose and demonstrate the development of an optical 2D accelerometer based on plastic optical fiber array using image detection for data analysis. The design is based in a light emitting diode coupled to a single POF working as a cantilever with an attached inertial mass. The output optical signal at the cantilever fiber is projected into a fiber array and acquired using a webcam. The use of image processing analysis allows the integration of the signal intensity in each fiber core and the estimation of the applied acceleration. © The Author(s) 2017.

关键词： Structural health monitoring

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Proceedings - International conference on image processing, ICIP

Proceedings - International Conference on Image Processing, ...

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24th IEEE International conference on image processing, ICIP 2017

ISBN: (纸本)9781509021758

The proceedings contain 923 papers. The topics discussed include: a novel angle-restricted test zone search algorithm for performance improvement of HEVC;probabilistic graphical model based fast HEVC inter prediction;motion compensation using critically sampled DWT subbands for low-bitrate video coding;multi-modal/multi-scale convolutional neural network based in-loop filter design for next generation video codec;robust plane-based calibration for linear cameras;exponential coordinates based rotation stabilization for panoramic videos;360-degree video stitching for dual-fisheye lens cameras based on rigid moving least squares;efficient cloud detection in remote sensing images using edge-aware segmentation network and easy-to-hard training strategy;robust ellipse detection via arc segmentation and classification;circle detection by arc-support line segments;face spoofing detection by fusing binocular depth and spatial pyramid coding micro-texture features;localized multi-kernel discriminative canonical correlation analysis for video-based person re-identification;on the accuracy and robustness of deep triplet embedding for fingerprint liveness detection;stereoscopic cloud base reconstruction using high-resolution whole sky imagers;person identification using spatiotemporal motion characteristics;blind quality assessment of multiply-distorted images based on structural degradation;and MVIRT, a toolbox for manifold-valued image restoration.

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