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检索条件"任意字段=2017 Conference on Design and Architectures for Signal and Image Processing, DASIP 2017"

共 891 条记录，以下是51-60 订阅

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Hardware/software co-design of dataflow programs for reconfigurable hardware and multi-core platforms

Hardware/software co-design of dataflow programs for reconfi...

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2011 conference on design and architectures for signal and image processing, dasip 2011

作者： Roquier, Ghislain Bezati, Endri Thavot, Richard Mattavelli, Marco Ecole Polytechnique Fédérale de Lausanne CH-1015 Lausanne Switzerland

ISBN: (纸本)9781457706196

The possibility of specifying both software and hardware components from a unified high-level description of an application is a very attractive design approach. However, despite the efforts spent for implementing such an approach using general purpose programming languages, it has not yet shown to be viable and efficient for complex designs. One of the reasons is that the sequential programming model does not naturally provide explicit and scalable parallelism and composability properties that effectively permits to build portable applications that can be efficiently mapped on different kind of heterogeneous platforms. Conversely dataflow programming is an approach that naturally provides explicit parallel programs with composability properties. This paper presents a methodology for the hardware/software co-design that enables, by direct synthesis of both hardware descriptions (HDL), software components (C/C++) and mutual interfaces, to generate an implementation of the application from an unique dataflow program, running onto heterogeneous architectures composed by reconfigurable hardware and multi-core processors. Experimental results based on the implementation of a JPEG codec onto an heterogeneous platform are also provided to show the capabilities and flexibility of the implementation approach. © 2011 IEEE.

关键词： Reconfigurable hardware

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Closed-loop Adaptive and Stochastic Prefetch Mechanism for Data Array 8

Closed-loop Adaptive and Stochastic Prefetch Mechanism for D...

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8th conference on design and architectures for signal and image processing (dasip)

作者： Vincent, Lionel Mancini, Stephane Grenoble Univ PERSYVAL Lab Grenoble France Grenoble Univ TIMA Lab Grenoble France

ISBN: (纸本)9791092279061

Nowadays, one of the main limiting factor in multiprocessor development is the increasing speed gap between efficient processing elements and slow main memories. To reduce this limitation, prefetching mechanisms, implemented in memory hierarchy, attempt to predict the future data needed in local memory. However, classical proposed solutions are no longer efficient for typical access sequences in the context of image processing algorithms. In this paper, a prefetching mechanism is proposed, based on the use of the index array of access rather than memory addresses. The adaptive prediction policy takes into account both application and main memory characteristics. This mechanism enhances the Cache nD-AP, formerly statically set, to improve its performance. Experiments show that the proposed adaptive strategy is able to maintain its efficiency when the characteristics of the system dynamically change.

关键词： prefetching Self tuning image processing algorithm memory hierarchy Access Memory storage allocation adaptive prediction main memory Local Memory

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Systemc modelization for fast validation of imager architectures

Systemc modelization for fast validation of imager architect...

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2011 conference on design and architectures for signal and image processing, dasip 2011

作者： Blanchard, Yves Dupret, Antoine Peizerat, Arnaud Paris-Est University ESYCOM ESIEE Paris Noisy le Grand France CEA LETI - MINATEC Grenoble France

ISBN: (纸本)9781457706196

Development of smart CMOS imagers is a complex design task where the verification of an architecture composed of a matrix of pixels intermixed with analog and digital electronics is playing an important part. New generations of imager using 3D integration will allow even more processing to be done in-situ. Verification has to be done locally for the pixel and globally for the architecture. design exploration and validation problematic has shifted from mostly the analog domain to the validation of a complex SOC with millions of parallel processors, the pixels. In this paper we present a methodology using the SystemC language for the creation of fast models for validation and a first level evaluation of performance of large CMOS imager architectures. © 2011 IEEE.

关键词： Pixels

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design of fixed-point rounding operators for the VHDL-2008 standard

Design of fixed-point rounding operators for the VHDL-2008 s...

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6th Annual conference on design and architectures for signal and image processing, dasip 2012

作者： Kavvadias, Nikolaos Masselos, Kostas Department of Computer Science and Technology University of Peloponnese 22100 Tripoli Greece

ISBN: (纸本)9782953998726

The contemporary design of sophisticated digital signal processing platforms involves the use of specifications at an increasingly raised abstraction level. This scheme is dictated by the ever growing divide between available circuit complexity and developer productivity. Algorithm developers tend to use very high-level programming languages such as MATLAB in order to rapidly and seamlessly generate low-level design facets such as ANSI C reference implementations and synthesizable HDL code. In this paper, a generic and parameterized implementation of fixed-point rounding operators in the VHDL hardware description language is introduced. Most hardware compilation frameworks either lack the support of these operators or provide specialized and non-portable implementations. Further, this is the first time that an implementation for these operators is being proposed, that can take advantage of features only present in the VHDL-2008 standard. Compared to existing fixed-point rounding, the proposed combinatorial designs achieve lower timing by about 30% with similar area demands for the case of signed arithmetic compared to rival designs when realized on FPGAs. © 2012 ECSI.

关键词： Computer hardware description languages

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Hybrid Prototyping Methodology for Rapid System Validation in HW/SW Co-design 13

Hybrid Prototyping Methodology for Rapid System Validation i...

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conference on design and architectures for signal and image processing (dasip)

作者： Wicaksana, Arief Charif, Amir Andriamisaina, Caaliph Ventroux, Nicolas CEA List Embedded Comp Lab F-91191 Gif Sur Yvette France

ISBN: (纸本)9781728140742

As the System-on-Chip (SoC) complexity increases, hardware/software co-design plays an important role to improve design productivity, reduce time to market, and optimize the overall results. Consequently, there is a high interest in providing rapid system validation in such a paradigm to achieve the aforementioned objectives. There exist in previous works prototyping techniques related to the development phase. FPGA-based prototyping has the benefits of enabling HW/SW integration and system validation after the Register Transfer Level (RTL) implementation is available while virtual platforms provide capabilities to accelerate software development with higher level functional models, e.g. Transaction Level Modeling (TLM). In this paper, we propose a hybrid prototyping methodology which takes advantage of virtual and FPGA-based prototyping in a single framework. We aim to provide a rapid and flexible system validation solution for HW/SW co-design at various stages of development based on the availability of TLM and RTL implementations. The proposed methodology allows online and offline performance analysis and debugging for early feedback in HW/SW architecture exploration. This was evaluated in the experiments with a neural network processor as a case study.

关键词： hybrid prototyping rapid system validation HW/SW co-design

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design of a matched filter for timing synchronization

Design of a matched filter for timing synchronization

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2013 7th conference on design and architectures for signal and image processing, dasip 2013

作者： Airoldi, Roberto Nurmi, Jari Tampere University of Technology Department of Electronics and Communications Engineering P.O. Box 553 Fin-33101 Tampere Finland

ISBN: (纸本)9791092279016

This paper presents the design and evaluation of two algorithms for the implementation of a matched filter for timing synchronization in receiver architectures. The proposed solutions reduce the complexity of the matched filter by at least 40% while maintaining the performance at an acceptable level. The designs were also compared to traditional matched filter design to evaluate their relative performance at different signal-to-noise-ratio (SNR) levels. Moreover, the designs were ported on a DSP-like core to analyse and evaluate their relative metrics, such as: computation time and energy consumption. Simulation results showed an energy and a computation time reduction of 60% and 40% respectively.

关键词： Matched filters

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Comparison of Lane Detection Algorithms for ADAS using Embedded Hardware architectures 12

Comparison of Lane Detection Algorithms for ADAS using Embed...

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12th conference on design and architectures for signal and image processing (dasip)

作者： Reichenbach, Marc Liebischer, Lukas Vaas, Steffen Fey, Dietmar Friedrich Alexander Univ Erlangen Nurnberg FAU Dept Comp Sci Chair Comp Architecture Erlangen Germany Friedrich Alexander Univ Erlangen Nurnberg FAU SDI Community Lab Erlangen Germany

ISBN: (纸本)9781538682371

Fast and robust lane detection algorithms are a fundamental technology for the development of advanced driver assistant systems (ADAS). Many projects in science and industry are using these kinds of algorithms. Unfortunately, algorithm implementations mainly focus on standard PC based hardware. If and how the processing can be realized on embedded devices in real-time is often not considered. Therefore, in this paper we present an extended evaluation of different optical based lane detection algorithms regarding both functional quality, and execution time on embedded devices. We compared five different lane detection algorithms for curved roads in combination with four different feature extraction filters. While the functional evaluation will be done by utilizing the F-measure metric, the execution time will be measured directly on embedded hardware. Furthermore, the algorithms were optimized to allow real-time processing. Our results show, that lane detection on images with a resolution of 1242 x 375 pixels can be done with up to 54 frames per second (fps) on an embedded ARM Cortex-A53 processor running at 1200 MHz.

关键词： Lane Line Detection Real-Time Autonomous Driving Energy Efficient Curved Lanes

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MARTE to ΠSDF transformation for data-intensive applications analysis 8

MARTE to ΠSDF transformation for data-intensive application...

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8th conference on design and architectures for signal and image processing (dasip)

作者： Ammar, Manel Baklouti, Mouna Pelcat, Maxime Desnos, Karol Abid, Mohamed Natl Engn Sch Sfax CES Lab Sfax Tunisia UEB IETR INSA Rennes CNRSUMR 6164 Rennes France

ISBN: (纸本)9791092279061

This paper proposes and validates a new methodology to facilitate the analysis of modern data-intensive applications. A major part of handling the processing needs of these applications consists in using the appropriate Model-ofComputation (MoC) which guarantees accurate performance estimations. Our methodology introduces one major contribution that facilitates the analysis step in the co-design flow. It is based on an intermediate level of abstraction implementing the Parameterized and Interfaced Synchronous Dataflow (Pi SDF) semantics. In the proposed methodology, a system designer models the embedded system using the standardised Modeling and Analysis of Real-Time and Embedded Systems (MARTE) profile. High-level models are then refined towards intermediate level models by following the Model-Driven Engineering (MDE) transformation paradigm. The model-to-model transformation permitting to reach the Pi SDF level starting from a MARTEcompliant model is detailed and validated in this paper. It is shown to facilitate system analysis.

关键词： Co-design MARTE Pi SDF MDE SoC

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Interfacing and scheduling legacy code within the canals framework

Interfacing and scheduling legacy code within the canals fra...

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2011 conference on design and architectures for signal and image processing, dasip 2011

作者： Dahlin, Andreas Jokhio, Fareed Lilius, Johan Gorin, Jérôme Raulet, Michaël Turku Centre for Computer Science Department of Information Technologies Åbo Akademi University Turku Finland IETR/Image Group Laboratory INSA Rennes Rennes France

ISBN: (纸本)9781457706196

The need for understanding how to distribute computations across multiple cores, have obviously increased in the multi-core era. Scheduling the functional blocks of an application for concurrent execution requires not only a good understanding of data dependencies, but also a structured way to describe the intended scheduling. In this paper we describe how the Canals language and its scheduling framework can be used for the purpose of scheduling and executing legacy code. Additionally a set of translation guidelines for translating RVC-CAL applications into Canals are presented. The proposed approaches are applied to an existing MPEG-4 Simple Profile decoder for evaluation purposes. The inverse discrete cosine transform (IDCT) is accelerated by the means of OpenCL. © 2011 IEEE.

关键词： Scheduling

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Acceleration of image reconstruction in 3D ultrasound computer tomography: An evaluation of CPU, GPU and FPGA computing

Acceleration of image reconstruction in 3D ultrasound comput...

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2011 conference on design and architectures for signal and image processing, dasip 2011

作者： Birk, Matthias Guth, Alexander Zapf, Michael Balzer, Matthias Ruiter, Nicole Hübner, Michael Becker, Jürgen Karlsruhe Germany

ISBN: (纸本)9781457706196

As today's standard screening methods frequently fail to diagnose breast cancer before metastases have developed, earlier breast cancer diagnosis is still a major challenge. Three-dimensional ultrasound computer tomography promises high-quality images of the breast, but is currently limited by a time-consuming synthetic aperture focusing technique based image reconstruction. In this work, we investigate the acceleration of the image reconstruction by a GPU, and by the FPGAs embedded in our custom data acquisition system. We compare the obtained performance results with a recent multi-core CPU and show that both platforms are able to accelerate processing. The GPU reaches the highest performance. Furthermore, we draw conclusions in terms of applicability of the accelerated reconstructions in future clinical application and highlight general principles for speed-up on GPUs and FPGAs. © 2011 IEEE.

关键词： Field programmable gate arrays (FPGA)

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