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conference on design and architectures for signal and image processing

作者： Jens Rettkowski David Gburek Diana Göhringer Application-Specific Multi-Core Architectures (MCA) Group Ruhr-University Bochum (RUB) Germany

Robotics combines a lot of different domains with sophisticated challenges such as computer vision, motion control and search algorithms. Search algorithms can be applied to calculate movements. The A* algorithm is a well-known and proved search algorithm to find a path within a graph. This paper presents an extended A* algorithm that is optimized for robot navigation using a bird's eye view as a map that is dynamically generated by image stitching. The scenario is a robot that moves to a target in an environment containing obstacles. The robot is controlled by a Xilinx Zynq platform that contains an ARM processor and an FPGA. In order to exploit the flexibility of such an architecture, the FPGA is used to execute the most compute-intensive task of the extended A* algorithm. This task is responsible for sorting the accessible nodes in the graph. Several environments with different complexity levels are used to evaluate the extended A* algorithm. The environment is captured by a Kinect sensor located directly on the robot. In order to dewarp the robot's view, the frames are transformed to a bird's eye view. In addition, a wider viewing range is achieved by image stitching. The evaluation of the extended A* algorithm shows a significant improvement in terms of memory utilization. Accordingly, this algorithm is especially practicable for embedded systems since they have often only limited memory resources. Moreover, the overall execution time for several use cases is reduced up to a speed-up of 2.88x.

关键词： Heuristic algorithms Navigation Cameras Robot vision systems Path planning

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Worst-case latency analysis of SDF-based parametrized dataflow MoCs

Worst-case latency analysis of SDF-based parametrized datafl...

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conference on design and architectures for signal and image processing

作者： Mladen Skelin Marc Geilen Francky Catthoor Sverre Hendseth Norwegian University of Science and Technology Eindhoven University of Technology MEC vzw

Modern-day streaming digital signal processing (DSP) applications are often accompanied by real-time requirements. In addition, they expose increasing levels of dynamic behavior. Dynamic dataflow models of computation (MoCs) have been introduced to model and analyze such applications. Parametrized dataflow MoCs are an important subclass of dynamic dataflow MoCs because they integrate dynamic parameters and run-time adaptation of parameters in a structured way. However, these MoCs have been primarily analyzed for functional behavior and correctness while the analysis of their temporal behavior has received little attention. In this work, we present a new analysis approach that allows analysis of worst-case latency for dynamic streaming DSP applications that can be captured using parametrized dataflow MoCs based on synchronous dataflow (SDF). We show that in the presence of parameter inter-dependencies our technique can yield tighter worst-case latency estimates than the existing techniques that operate on SDF structures that abstract the worst-case behaviour of the initial parametrized specifications. We base the approach on the (max,+) algebraic semantics of timed SDF and on its non-parametric generalization known as FSM-based scenario-aware dataflow (FSM-SADF). We evaluate the approach on a realistic case study from the multimedia domain.

关键词： Decoding Delays Digital signal processing Computational modeling Multimedia communication Adaptation models Streaming media

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Real-time correlation for locating systems utilizing heterogeneous computing architectures

Real-time correlation for locating systems utilizing heterog...

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conference on design and architectures for signal and image processing

作者： Marc Reichenbach Max Kasparek Mohammad Alawieh Konrad Häublein Dietmar Fey Department Computer Science Friedrich-Alexander-Universitat Erlangen-Niirnberg (FAU) Fraunhofer Institut fur integrierte Schaltungen (IIS)

The usage of locating systems in sports (e.g. soccer) elevates match and training analysis to a new level. By tracking players and balls during matches or training, the performance of players can be analyzed, the training can be adapted and new strategies can be developed. The radio-based RedFIR system equips players and the ball with miniaturized transmitters, while antennas distributed around the playing field receive the transmitted radio signals. A cluster computer processes these signals to determine the exact positions based on the signals' Time Of Arrival (TOA) at the back end. While such a system works well, it is neither scalable nor inexpensive due to the required computing cluster. Also the relatively high power consumption of the GPU-based cluster is suboptimal. Moreover, high speed interconnects between the antennas and the cluster computers introduce additional costs and increase the installation effort. However, a significant portion of the computing performance is not required for the synthesis of the received data, but for the calculation of the unique TOA values of every receiver line. Therefore, in this paper we propose a smart sensor approach: By integrating some intelligence into the antenna (smart antenna), each antenna can correlate the received signal independently of the remaining system and only TOA values are send to the backend. While the idea is quite simple, the question of a well suited computer architecture to fulfill this task inside the smart antenna is more complex. Therefore, we are evaluating embedded architectures, such as FPGAs, ARM cores as well as a many core CPU (Epiphany) for this approach. Thereby, we are able to achieve 50.000 correlations per second in each smart antenna. As a result, the backend becomes lightweight, cheaper interconnects through data reduction are required and the system becomes more scalable, since most processing power is already included in the antenna.

关键词： Computer architecture Correlation Antennas Field programmable gate arrays Intelligent sensors Receivers Hardware

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Parallel Monte Carlo Search for Hough Transform

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Journal of Physics: conference Series 2017年第7期898卷

作者： Raul H. C. Lopes Virginia N.L. Franqueira Ivan D. Reid Peter R. Hobson College of Engineering Design and Physical Sciences Brunei University London Uxbridge UB8 3PH UK College of Engineering and Technology University of Derby Derby DE22 1GB UK

We investigate the problem of line detection in digital image processing and in special how state of the art algorithms behave in the presence of noise and whether CPU efficiency can be improved by the combination of a Monte Carlo Tree Search, hierarchical space decomposition, and parallel computing. The starting point of the investigation is the method introduced in 1962 by Paul Hough for detecting lines in binary images. Extended in the 1970s to the detection of space forms, what came to be known as Hough Transform (HT) has been proposed, for example, in the context of track fitting in the LHC ATLAS and CMS projects. The Hough Transform transfers the problem of line detection, for example, into one of optimization of the peak in a vote counting process for cells which contain the possible points of candidate lines. The detection algorithm can be computationally expensive both in the demands made upon the processor and on memory. Additionally, it can have a reduced effectiveness in detection in the presence of noise. Our first contribution consists in an evaluation of the use of a variation of the Radon Transform as a form of improving theeffectiveness of line detection in the presence of noise. Then, parallel algorithms for variations of the Hough Transform and the Radon Transform for line detection are introduced. An algorithm for Parallel Monte Carlo Search applied to line detection is also introduced. Their algorithmic complexities are discussed. Finally, implementations on multi-GPU and multicore architectures are discussed.

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dasip 2013 - Proceedings of the 2013 conference on design and architectures for signal and image processing

DASIP 2013 - Proceedings of the 2013 Conference on Design an...

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2013 7th conference on design and architectures for signal and image processing, dasip 2013

ISBN: (纸本)9791092279016

The proceedings contain 53 papers. The topics discussed include: high performance multi-standard architecture for DCT computation in H.264/AVC high profile and HEVC codecs;architecture and programming model support for efficient heterogeneous computing on tightly-coupled shared-memory clusters;a neural model for hardware plasticity in artificial vision systems;system-level PMC-driven energy estimation models in RVC-CAL video codec specifications;a resource-aware nearest neighbor search algorithm for k-dimensional trees;accuracy and performance analysis of Harris corner computation on tightly-coupled processor arrays;a linear state model for PDR+WLAN positioning;SiPM based smart pixel for photon counting integrated streak camera;a coarse-grained reconfigurable wavelet denoiser exploiting the multi-dataflow composer tool;foreground object features extraction with GLCM texture descriptor in FPG;and noise-agnostic adaptive image filtering without training references on an evolvable hardware platform.

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A Review of World's Fastest Connected Component Labeling Algorithms: Speed and Energy Estimation 8

A Review of World's Fastest Connected Component Labeling Alg...

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8th conference on design and architectures for signal and image processing (dasip)

作者： Cabaret, Laurent Lacassagne, Lionel Oudni, Louiza Univ Paris Sud Lab Rech Informat F-91405 Orsay France

ISBN: (纸本)9791092279061

Optimizing connected component labeling is currently a very active research field. The current most effective algorithms although close in their design are based on different memory/computation trade-offs. This paper presents a review of these algorithms and a detailed benchmark on several Intel and ARM embedded processors that allows to focus on their advantages and drawbacks and to highlight how processor architecture impact them.

关键词： connected component algorithms Processor architectures

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Welcome to the 2013 conference on design and architectures for signal and image processing (dasip) in Cagliari, Italy

Conference on Design and Architectures for Signal and Image ...

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conference on design and architectures for signal and image processing, dasip 2013年 8-8页

作者： Meloni, Paolo Jego, Christophe

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Video++, a modern image and video processing C++ framework 8

Video++, a modern image and video processing C++ framework

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2014 8th conference on design and architectures for signal and image processing, dasip 2014

作者： Garrigues, Matthieu Manzanera, Antoine ENSTA-ParisTech 828 Boulevard des Maréchaux Palaiseau Cedex91762 France

ISBN: (纸本)9791092279054

We present in this paper Video++, a new framework targeting image and video applications running on multi-core processors. While offering a high expressive power, we show that it generates code running up to 32 times faster than the naive equivalents. Taking advantage of the new C++11/C++14 features, tools, we propose simple abstractions matching the performance of hand optimized code. This paper gives an overview of the library and demonstrates its efficiency with some benchmarks. © 2014 European Electronic Chips & Systems design Initiative - ECSI.

关键词： Video signal processing

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Hardware Architecture design and Implementation for FMCW Radar signal processing Algorithm 8

Hardware Architecture Design and Implementation for FMCW Rad...

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8th conference on design and architectures for signal and image processing (dasip)

作者： Eugin, Hyun Lee, Jonghun DGIST ART Adv Radar Technol Lab Robot Res Div Daegu South Korea

ISBN: (纸本)9791092279061

Chirp-sequence-based Frequency Modulation Continuous Wave (FMCW) radar is effective at detecting range and velocity of a target. However, the target detection algorithm is based on two-dimensional Fast Fourier Transform, which uses a great deal of data over several PRIs (Pulse Repetition Intervals). In particular, if the multiple-receive channel is employed to estimate the angle position of a target;even more computational complexity is required. In this paper, we report on how a newly developed signal processing module is implemented in the FPGA, and on its performance measured under test conditions. Moreover, we have presented results from analysis of the use of hardware resources and processing times.

关键词： FMCW radar detection algorithm chirp sequence

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PHAT: A TECHNOLOGY FOR PROTOTYPING PARALLEL HETEROGENEOUS architectures 8

PHAT: A TECHNOLOGY FOR PROTOTYPING PARALLEL HETEROGENEOUS AR...

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8th conference on design and architectures for signal and image processing (dasip)

作者： Wink, Thorsten Koch, Andreas Tech Univ Darmstadt Embedded Syst & Applicat Grp Darmstadt Germany

ISBN: (纸本)9791092279061

This paper presents the Parallel Heterogeneous Architecture Technology (PHAT), a scalable design methodology for prototyping and evaluating heterogeneous arrays of software-programmable VLIW processors and both manually designed and automatically-compiled custom hardware accelerators, using a shared memory architecture for communication. We discuss the trade-offs and break-even point for switching from bus-based to network-on-chip interconnects, the interface and protocols for connecting distributed on-chip caches and multi-bank out-of-order offchip- memories, as well as the impact of floorplanning on the quality of results for implementation on Xilinx Virtex 6 LX 760 devices. The capabilities are evaluated at the system-level on the multi-FPGA Convey HC-1ex hybrid-core computer, accessing its high-performance memory system, and integrating r-VEX processor cores with IP blocks for SHA and FFT computations.

关键词： on-chip cache shared memory systems PROTOTYPE circuit layout Secure Hashing Algorithm ARCHITECTURE EIS IMPLEMENTATION PLANS PROCESSOR protocols Parallel Lines Memory architecture system level BREAKEVEN

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