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检索条件"任意字段=2017 Conference on Design and Architectures for Signal and Image Processing, DASIP 2017"

共 891 条记录，以下是71-80 订阅

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Low Power design Methodology for signal processing Systems using Lightweight Dataflow Techniques

Low Power Design Methodology for Signal Processing Systems u...

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conference on design and architectures for signal and image processing (dasip)

作者： Li, Lin Fanni, Tiziana Viitanen, Timo Xie, Renjie Palumbo, Francesca Raffo, Luigi Huttunen, Heikki Takala, Jarmo Bhattacharyya, Shuvra S. Univ Maryland ECE Dept College Pk MD 20742 USA Univ Cagliari Dept Elect & Elect Engn Cagliari Italy Tampere Univ Technol Tampere Finland Univ Sassari PolComIng Informat Engn Unit Sassari Italy

ISBN: (纸本)9791092279153

Dataflow modeling techniques facilitate many aspects of design exploration and optimization for signal processing systems, such as efficient scheduling, memory management, and task synchronization. The lightweight dataflow (LWDF) programming methodology provides an abstract programming model that supports dataflow-based design and implementation of signal processing hardware and software components and systems. Previous work on LWDF techniques has emphasized their application to DSP software implementation. In this paper, we present new extensions of the LWDF methodology for effective integration with hardware description languages (HDLs), and we apply these extensions to develop efficient methods for low power DSP hardware implementation. Through a case study of a deep neural network application for vehicle classification, we demonstrate our proposed LWDF-based hardware design methodology, and its effectiveness in low power implementation of complex signal processing systems.

关键词： Deep neural networks

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Model-Driven design flow for distributed control in reconfigurable FPGA systems 8

Model-Driven design flow for distributed control in reconfig...

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8th conference on design and architectures for signal and image processing (dasip)

作者： Trabelsi, Chiraz Meftali, Samy ben Atitallah, Rabie Dekeyser, Jean-Luc Univ Valenciennes LAMIH Valenciennes France Univ Lille 1 LIFL INRIA Lille Nord Europe Lille France

ISBN: (纸本)9791092279061

One of the most challenging and time-consuming design tasks for dynamically reconfigurable FPGA (Field Programmable Gate Array) systems is the design of runtimeadaptation control. This aspect covers various points such as runtime-monitoring, reconfiguration decision-making and reconfiguration realization. In this paper, we propose a control design flow aiming at facilitating the designers work and enhancing their productivity through high design reuse and automation. The proposed flow combines control distribution and Model-Driven-Engineering (MDE). The distributed control structure proposed in this flow aims at facilitating the reuse of the control design by using separate controllers for local and global control problems. The flow enables designers to move from high-level control models, using an extended version of the MARTE (Modeling and Analysis of Real-Time and Embedded Systems) UML standard profile, to an automatic generation of the corresponding VHDL code. The flow was validated through a video processing case study from modeling to implementation in FPGA.

关键词： UML MARTE Model-Driven-Engineering distributed control Partial Dynamic Reconfiguration FPGA

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Application of temporal decoupling to the creation of efficient performance models of automotive architectures

Application of temporal decoupling to the creation of effici...

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6th Annual conference on design and architectures for signal and image processing, dasip 2012

作者： Majdoub, Takieddine Le Nours, Sebastien Pasquier, Olivier Nouvel, Fabienne Univ Nantes IETR UMR 6164 Polytech-Nantes rue C. Pauc Nantes F-44000 France INSA Rennes IETR UMR 6164 20 avenue des Buttes de Coësmes 35043 Rennes France

ISBN: (纸本)9782953998726

Due to the increasing complexity of communication infrastructures in the automotive domain, reliable models of embedded system architectures are necessary in order to assist designers in the development process. In this context, transaction level modeling, supported by languages as SystemC, is a promising solution to allow performances of networked architectures to be assessed with different compromise between accuracy and simulation speed. In this paper, a modeling technique is proposed to improve the simulation speed of architecture models used for performance evaluation. A specific case study inspired from the automotive domain is used to illustrate how simulation speed-up is achieved using the proposed technique. A significant simulation speed up by an order of magnitude of 100 is achieved in the considered case study. © 2012 ECSI.

关键词： Modeling languages

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Implementation of a real-time image-based vibration detection and adaptive filtering on an FPGA 12

Implementation of a real-time image-based vibration detectio...

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12th conference on design and architectures for signal and image processing (dasip)

作者： Uetsuhara, Kazuya Tahara, Akanae Manabe, Taito Shibata, Yuichiro Nagasaki Univ Grad Sch Engn Nagasaki Japan

ISBN: (纸本)9781538682371

In this paper, we propose and implement a field-programmable gate array (FPGA) system which extracts a vibration component of a desired frequency band from moving images in real-time, aiming at application to image-based vibration suppression such as microsurgery assistance systems. The technical challenges to this end are two-fold: fast and robust detection of vibration components in given moving images and zero-phase band-pass filtering for a desired frequency band. For the former, we employ a statistical approach using dense optical flow to derive frequency components, and design a custom optical flow computing hardware with the Lucas-Kanade (LK) method. For the latter, we implement a sort of adaptive band-pass filters called a bandlimited multiple Fourier linear combiner (BMFLC), which can recompose input signals as a mixture of sinusoidal signals with multiple frequencies in a band with no phase delay. Both designs are implemented in a deeply pipelined manner on a Xilinx Kintex-7 XC325T FPGA, without using any external memories. Empirical experiments reveal that the proposed system extracts a vibration component of high-frequency tremors in hand motions, while intentional low-frequency motions are successfully filtered out. The system processes VGA moving images at 60 fps, with a delay of less than 1 us for the BMFLC, suggesting effectiveness of the deep pipelined architecture.

关键词： Optical imaging Optical attenuators Vibrations Optical sensors Real-time systems Surgery Field programmable gate arrays

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Turnus: A unified dataflow design space exploration framework for heterogeneous parallel systems

Turnus: A unified dataflow design space exploration framewor...

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2013 7th conference on design and architectures for signal and image processing, dasip 2013

作者： Casale-Brunet, Simone Alberti, Claudio Mattavelli, Marco Janneck, Jorn W. EPFL SCI-STI-MM École Polytechnique Fédérale de Lausanne Switzerland Department of Computer Science Lund University Sweden

ISBN: (纸本)9791092279016

This paper presents the main features of the TURNUS co-exploration environment, an unified design space exploration framework suitable for heterogeneous parallel systems designed using an high level dataflow representation. The main functions of this tool are illustrated through the analysis of a video decoder implemented in the RVC-CAL dataflow language.

关键词： Data flow analysis

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Architectural decomposition of video decoders for many core architectures

Architectural decomposition of video decoders for many core ...

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6th Annual conference on design and architectures for signal and image processing, dasip 2012

作者： Richter, Henryk Stabernack, Benno Kuhn, Volker Institute of Communications Engineering University of Rostock Richard-Wagner-Str. 31 Rostock 18119 Germany Department of Image Processing Fraunhofer Institute for Telecommunications Heinrich-Hertz-Institut Berlin 10587 Germany

ISBN: (纸本)9782953998726

The microprocessor industry trend towards many-core architectures introduced the necessity of devising appropriately scalable applications. In video decoding, the main challenges are the optimized partitioning of decoder operations, efficient tracking of dependencies and resource allocation/ synchronization for multiple threads. In this paper, we propose a decoder architecture that replaces the conventional monolithic design with a pipelined structure. Bit stream decoding and image processing are separated from each other by means of a Meta Format Stream. The Meta Format is forward-oriented and self contained and multistandard capable, so that processing of Meta Streams is independent of the originating bit stream. Our approach does not require special coding settings and is applicable to accelerated decoding of any standards-compliant bit stream. A H.264 multiprocessing proposal is presented as a case study for the potential our our decoder architecture. The case study combines coarse grained frame-level parallel decoding of the bit stream with fine-grained macroblock level parallelism in the image processing stage. The proposed H.264 decoder achieved speedup factors of up to 7.6 on an 8 core machine with 2-way SMT. We are reporting actual decoding speeds of up to 150 frames per second in 2160p-resolution. © 2012 ECSI.

关键词： Decoding

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On the scalability of image and signal processing parallel applications on emerging cc-NUMA many-cores

On the scalability of image and signal processing parallel a...

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6th Annual conference on design and architectures for signal and image processing, dasip 2012

作者： Almaless, Ghassan Wajsburt, Franck LIP6 UPMC Sorbonne Universités 4 place Jussieu Paris France

ISBN: (纸本)9782953998726

Nowadays, single-chip cache-coherent multi-cores up to 100 cores are a reality and many-cores of hundreds of cores are planned in the near future. This technological shift undertaking by the high-end computer-industry is converging with the design motivation of other domains like embedded and HPC industries. In this paper, we propose to investigate the scalability of the same four unmodified, shared-memory, image and signal processing oriented parallel applications on two targets: (i) embedded - TSAR, a single-chip 256-cores based, Cycle-Accurate-Bit-Accurate simulated, cc-NUMA many-core;and (ii) high-end - an AMD Opteron Interlagos, 64-core based, cc-NUMA many-core. Beside our scalability results on both cc-NUMA targets, our contributions include two operating system mechanisms: (i) a distributed, client/server based, scheduler design allowing the kernel to offer scalable inter-threads synchronization mechanisms;and (ii) a kernel-level memory affinity technique named Auto-Next-Touch allowing the kernel to transparently and automatically migrate physical pages in order to enforce the locality of thread's memory accesses. Although these two mechanisms are implemented and evaluated in ALMOS (Advanced Locality Management Operating System) running on the TSAR target, they remain applicable to other shared-memory operating systems. © 2012 ECSI.

关键词： image processing

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Development of a method for image-based motion estimation of a VTOL-MAV on FPGA

Development of a method for image-based motion estimation of...

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2011 conference on design and architectures for signal and image processing, dasip 2011

作者： Frietsch, N. Pashkovskiy, I. Trommer, G.F. Braun, L. Birk, M. Hübner, M. Becker, J. Karlsruhe Germany Karlsruhe Germany

ISBN: (纸本)9781457706196

In this paper, the development of the vision based motion estimation for a small-scale VTOL-MAV as well as the implementation on FPGA are investigated. Especially in urban environments the GPS signal quality is disturbed by shading and multipath propagation and an augmentation with another sensor is inevitable. The vision system bases on the analysis of the sparse optical flow that is extracted from images taken by the onboard camera. From the extracted point correspondences projective transformations are estimated with a robust parameter estimation algorithm. As the underlying image processing routines are computationally expensive but can be processed in parallel they have been implemented on FPGA. The different parts of the algorithm as well as the implementation are covered in detail. © 2011 IEEE.

关键词： Optical flows

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image Tiling for Embedded Applications with Non-Linear Constraints

Image Tiling for Embedded Applications with Non-Linear Const...

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conference on design and architectures for signal & image processing

作者： Schwambach, Vitor Cleyet-Merle, Sebastien Issard, Alain Mancini, Stephane Univ Grenoble Alpes TIMA F-38031 Grenoble France CNRS TIMA F-38031 Grenoble France STMicroelectronics Grenoble France

ISBN: (纸本)9791092279115

Tiling is a key aspect of the design of embedded image processing applications, due to local memory constraints. To maximize system performance, the designer must select a suitable tile size that balances data transfers and computation. In this work, we present a method for optimal 2D image tile sizing using constraint programming. Unlike previous methods, ours accurately models DMA data transfer times and parallel scheduling overheads with non-linear constraints. Our experiments with a binomial filter demonstrate that we can compute the optimal tiling dimensions that minimize the execution time for different image sizes and internal memory constraints. This technique provides invaluable information for both application developers and system architects that can quickly explore design trade-offs.

关键词： Modeling design Optimization image processing Embedded Software

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Demonstrating a Dataflow-based RTOS for Heterogeneous MPSoC by means of a Stereo Matching Application 8

Demonstrating a Dataflow-based RTOS for Heterogeneous MPSoC ...

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8th conference on design and architectures for signal and image processing (dasip)

作者： Heulot, Julien Menant, Judicael Pelcat, Maxime Nezan, Jean-Francois Morin, Luce Pressigout, Muriel Aridhi, Slaheddine UEB CNRS UMR 6164 INSA Rennes IETR 20 Ave Buttes de Coesmes Rennes France Texas Instruments France Cagnes Sur Mer France

ISBN: (纸本)9791092279061

This demonstration paper presents a multicore Real Time Operating System (RTOS) that schedules a parameterized dataflow Model of Computation (MoC) onto a multicore Digital signal Processor (DSP) at runtime. This RTOS called Synchronous Parameterized and Interfaced Dataflow Embedded Runtime (SPIDER) exploits the Parameterized and Interfaced Synchronous Dataflow (PiSDF) MoC and its features at runtime to identify locally static regions and to optimize their execution onto multicore platforms. The RTOS is used to dispatch a stereo matching algorithm tasks with a varying range of disparities. The platform used for this demonstration is a Texas Instruments Keystone II Multiprocessor System-on-Chip (MPSoC) device composed of 8 DSP cores, 4 ARM cores, a shared memory subsystem, Multicore Navigator and multiple dedicated accelerators.

关键词： Multi-core processors parameterization Runtime data flow Legal Executions Digital signal processing Desmoplakin Gene

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