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检索条件"任意字段=2017 Conference on Design and Architectures for Signal and Image Processing, DASIP 2017"

共 891 条记录，以下是791-800 订阅

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An experimental toolchain based on high-level dataflow models of computation for heterogeneous MPSoC

An experimental toolchain based on high-level dataflow model...

引用

6th Annual conference on design and architectures for signal and image processing, dasip 2012

作者： Heulot, J. Desnos, K. Nezan, J.-F. Pelcat, M. Raulet, M. Yviquel, H. Lagalaye, P.-L. Le Lann, J.-C. INSA IETR UMR 6164 UEB 20 av. Buttes de Coësmes 35708 Rennes France IRISA Univ. Rennes 1 6 rue de Kerampont 22300 Lannion France Modaë Technologies 16 Rue Isaac Le Chapelier 35000 Rennes France Labsticc-ENSTA Bretagne France

A chain of three state-of-the-art tools is demonstrated to generate efficient code for Multi-Processors System-on-Chips (MPSoCs) from a high-level dataflow language. The experimental platform is based on a 5-core Texa... 详细信息

ISBN: (纸本)9782953998726

关键词： image processing

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design under constraints of availability and energy for sensor node in wireless sensor network

Design under constraints of availability and energy for sens...

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6th Annual conference on design and architectures for signal and image processing, dasip 2012

作者： Hoang, Van-Trinh Julien, Nathalie Berruet, Pascal Lab-STICC/University of South-Brittany Research Center BP 92116 56321 Lorient France

ISBN: (纸本)9782953998726

Wireless Sensor Network (WSN) technology has been getting a lot of attention in recent years due to its low-cost, portability, easy deployment, self-organisation, and reconfigurability. Two main challenges faced by designers are availability and power/energy management for WSN. This paper presents a design for a wireless sensor node, which provides automated reconfiguration for both availability and energy-efficient use. This design introduces an original device named Power and Availability Manager (PAM) combined with a FPGA. The first one is considered as the intelligent part for the best use of energy and fault-tolerance, while the other enhances the availability in case of hardware failure for a node. Simulation model of these solutions together is based on General Stochastic Petri Net (GSPN). The results indicate a gain of availability from 9% to 31% for sensor node over twelve years, from 9% to 46% for sensor cluster over eighteen years, from 11% to 45% for whole network over fifty years. Our approach also results in significant energy-saving : up to 61% by using DPM policy, and up to 62.5% by using DPM and DVFS policies over seven days. These results allow us to evaluate and to show a design of WSN node for increased availability as well as energy-saving by using our approach. © 2012 ECSI.

关键词： Energy efficiency

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design space exploration strategies for FPGA implementation of signal processing systems using CAL dataflow program

Design space exploration strategies for FPGA implementation ...

引用

6th Annual conference on design and architectures for signal and image processing, dasip 2012

作者： Rahman, Ab Al-Hadi Ab Thavot, Richard Brunet, Simone Casale Bezati, Endri Mattavelli, Marco SCI-STI-MM École Polytechnique Fédérale de Lausanne Station 11 CH-1015 Lausanne Switzerland

ISBN: (纸本)9782953998726

This paper presents some strategies for design space exploration of FPGA-based signal processing systems that are specified using the CAL dataflow language. The actor-oriented, high-level of abstraction provided by CAL allows flexible exploration and consequently results in a wide range of feasible design implementations. We have applied and extended the existing techniques for refactoring and pipelining actors and actions by means of critical path analysis, and introduced some new buffering techniques based on heuristics. The combinations of these techniques have been applied on the CAL specification of the MPEG-4 video decoder, and synthesized to HDL for evaluation in the design implementation space. Results show that using our configuration for the exploration of 48 design points, a throughput range of roughly 8× has been achieved, for slice, block RAM, frequency, and latency range of 1.3×, 2.5×, 2.5×, and 2.9× respectively. © 2012 ECSI.

关键词： Field programmable gate arrays (FPGA)

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design of fixed-point embedded systems (DEFIS) French ANR project

Design of fixed-point embedded systems (DEFIS) French ANR pr...

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6th Annual conference on design and architectures for signal and image processing, dasip 2012

作者： Menard, D. Rocher, R. Sentieys, O. Simon, N. Didier, L.-S. Hilaire, T. Lopez, B. Goubault, E. Putot, S. Vedrine, F. Najahi, A. Revy, G. Fangain, L. Samoyeau, C. Lemonnier, F. Clienti, C. University of Rennes i IRISA/INRIA 6 rue de kerampont F-22300 Lannion France University Pierre et Marie Curie LIP6 4 place Jussieu F-75005 Paris France CEA LIST Saclay Nano-INNOV Point Courrier no 174 F-91191 Gif sur Yvette France Univ. Perpignan Via Domitia DALI/LIRMM F-66860 Perpignan France InPixal 80 Avenue des Buttes de Cosmes F-35700 Rennes France Thales TRandT Route Departementale F-91120 Palaiseau France

ISBN: (纸本)9782953998726

Embedded applications are usually coming with stringent constraints in term of cost, energy consumption and realtime. Consequently, fixed-point arithmetic is mainstream for their implementation into embedded systems. Hence, the main objective of the french ANR project DEFIS is to provide a complete design flow for fixed-point refinement of complex applications. This tool flow is like the missing link between high-level application specification tools and low-level implementation. © 2012 ECSI.

关键词： Embedded systems

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designing processors using MAsS, a modular and lightweight instruction-level exploration tool

Designing processors using MAsS, a modular and lightweight i...

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2011 conference on design and architectures for signal and image processing, dasip 2011

作者： Texier, Matthieu Piriou, Erwan Thevenin, Mathieu David, Raphaël CEA LIST Embedded Computing Laboratory - PC94 F91191 Gif sur Yvette France

ISBN: (纸本)9781457706196

As application complexity increases, the design of efficient computing architectures able to cope with embedded constraints requires a fine algorithm analysis. This paper proposes an original approach based on Modular Assembly Simulator (MAsS) tool that allows design Space Exploration (DSE) for programmable processors. The originality of the method resides in its capacity to generate operator level simulators allowing a quick code analysis from real data sets. This paper also presents two successfully designed architectures using MAsS. © 2011 IEEE.

关键词： Integrated circuit design

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A framework for the design of reconfigurable fault tolerant architectures

A framework for the design of reconfigurable fault tolerant ...

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2011 conference on design and architectures for signal and image processing, dasip 2011

作者： Pham, Hung Manh Pillement, Sébastien Pasquier, Olivier Le Nours, Sébastien University of Rennes I IRISA 6 rue de Kerampont 22302 Lannion France IREENA - Polytech Nantes Rue Christian Pauc 44306 Nantes Cedex 3 France

ISBN: (纸本)9781457706196

The rapid evolutions in reconfigurable electronic products design permit to handle more and more complex applications. New fields of investigations (i.e. automotive, aerospatial, banking,...) are interesting but require a high level of dependability. This paper proposes a framework to design reconfig-urable architecture supporting fault-tolerance mitigation scheme. The proposed framework allows simulation, validation of mitigation operations, but also to size architecture resources. The implementation of a fault-tolerant reconfigurable platform permits to validate the proposed model and the effectiveness of the framework. This implementation shows the potential of dynamically reconfigurable architectures for supporting fault-tolerance in embedded systems. © 2011 IEEE.

关键词： Fault tolerance

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The multi-dataflow composer tool: A runtime reconfigurable HDL platform composer

The multi-dataflow composer tool: A runtime reconfigurable H...

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2011 conference on design and architectures for signal and image processing, dasip 2011

作者： Palumbo, Francesca Carta, Nicola Raffo, Luigi DIEE - Dept. of Electrical and Electronic Engineering University of Cagliari P.zza D'Armi 09123 Cagliari Italy

ISBN: (纸本)9781457706196

Dataflow Model of Computation (D-MoC) is particularly suitable to close the gap between hardware architects and software developers. Leveraging on the combination of the D-MoC with a coarse-grained reconfigurable approach to hardware design, we propose a tool, the Multi-Dataflow Composer (MDC) tool, able to improve time-to-market of modern complex multi-purpose systems by allowing the derivation of HDL runtime reconfigurable platforms starting from the D-MoC models of the targeted set of applications. MDC tool has proven to provide a considerable on-chip area saving: the 82% of saving has been reached combining of different applications in the image processing domain, adopting a 90 nm CMOS technology. In future the MDC tool, with a very small integration effort, will also be extremely useful to create multi-standard codec platforms for MPEG RVC applications. © 2011 IEEE.

关键词： image processing

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High level design of adaptive distributed controller for partial dynamic reconfiguration in FPGA

High level design of adaptive distributed controller for par...

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2011 conference on design and architectures for signal and image processing, dasip 2011

作者： Cherif, Sana Trabelsi, Chiraz Meftali, Samy Dekeyser, Jean-Luc INRIA Lille Nord Europe LIFL USTL 40 avenue Halley 59650 Villeneuve d'Ascq France

ISBN: (纸本)9781457706196

Controlling dynamic and partial reconfigurations becomes one of the most important key issues in modern embedded systems design. In fact, in such systems, the reconfiguration controller can significantly affect the system performances. Indeed, the controller has to handle efficiently three major tasks during runtime: observation (monitoring), taking reconfiguration decisions and notify decisions to the rest of the system in order to realize it. We present in this paper a novel high level approach permitting to model, using MARTE UML profile, modular and flexible distributed controllers for dynamic reconfiguration management. This approach permits components/ models reuse and allows systematic code generation. It consequently makes reconfigurable systems design less tedious and reduces time to market. © 2011 IEEE.

关键词： Controllers

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Application workload model generation methodologies for system-level design exploration

Application workload model generation methodologies for syst...

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2011 conference on design and architectures for signal and image processing, dasip 2011

作者： Saastamoinen, Jukka Kreku, Jari Communication Platforms VTT Technical Research Centre of Finland Kaitoväylä 1 FI-90571 Oulu Finland

ISBN: (纸本)9781457706196

As most of the applications of embedded system products are realized in software, the performance estimation of software is crucial for successful system design. Significant part of the functionality of these applications is based on services provided by the underlying software libraries. Often used performance evaluation technique today is the system-level performance simulation of the applications and platforms using abstracted workload and execution platform models. The accuracy of the software performance results is dependent on how closely the application workload model reflects actual software as a whole. This paper presents a methodology which combines compiler based user code workload model generation with workload extraction of pre-compiled libraries, while exploiting an overall approach and execution platform model developed previously. Benefit of the proposed methodology compared to earlier solution is experimented using a set of benchmarks. © 2011 IEEE.

关键词： Application programs

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Development of a method for image-based motion estimation of a VTOL-MAV on FPGA

Development of a method for image-based motion estimation of...

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2011 conference on design and architectures for signal and image processing, dasip 2011

作者： Frietsch, N. Pashkovskiy, I. Trommer, G.F. Braun, L. Birk, M. Hübner, M. Becker, J. Karlsruhe Germany Karlsruhe Germany

ISBN: (纸本)9781457706196

In this paper, the development of the vision based motion estimation for a small-scale VTOL-MAV as well as the implementation on FPGA are investigated. Especially in urban environments the GPS signal quality is disturbed by shading and multipath propagation and an augmentation with another sensor is inevitable. The vision system bases on the analysis of the sparse optical flow that is extracted from images taken by the onboard camera. From the extracted point correspondences projective transformations are estimated with a robust parameter estimation algorithm. As the underlying image processing routines are computationally expensive but can be processed in parallel they have been implemented on FPGA. The different parts of the algorithm as well as the implementation are covered in detail. © 2011 IEEE.

关键词： Optical flows

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