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Compressed sensing image reconstruction based on joint statistical and structural priors

Compressed sensing image reconstruction based on joint stati...

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International conference on Advanced Communication Technology (ICACT)

作者： Jiahui Li Shaohua Wu Huan Huang Jian Jiao Harbin Institute a/Technology Shenzhen Graduate School Shenzhen Guangdong China

ISBN: (纸本)9781509048922

Due to proper use of the image sparsity, CS (compressed sensing) image compression has made great achievements in the field of image compression without the constraint of Nyquist sampling law. A great deal of researches indicate that there exist obvious statistical and structural priors regularity for image information distribution, while traditional CS image compression algorithms only use the sparse characteristic of the image information. In this paper, we propose a CS image reconstruction algorithm based on the joint statistical and structural priors which can achieve efficient image reconstruction via a small amount of measurements. With the full use of inter-scale and intra-scale relations of the sparse coefficients, we optimize the iterative hard thresholding CS algorithm specifically by building a GSM model to constrain the local coefficients distribution statistically, and a tree model to constrain the global coefficients distribution structurally. Extensive simulations have been conducted and the results show that the proposed method has achieved a considerable promotion both on the speed and the PSNR gain of image reconstruction, compared with the traditional recovery algorithms under the same compression ratio.

关键词： image reconstruction image coding Algorithm design and analysis signal processing algorithms Matching pursuit algorithms Wavelet coefficients GSM

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Cambricon-S: Addressing Irregularity in Sparse Neural Networks through A Cooperative Software/Hardware Approach 51

Cambricon-S: Addressing Irregularity in Sparse Neural Networ...

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51st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)

作者： Zhou, Xuda Du, Zidong Guo, Qi Liu, Shaoli Liu, Chengsi Wang, Chao Zhou, Xuehai Li, Ling Chen, Tianshi Chen, Yunji Univ Sci & Technol China Hefei Anhui Peoples R China Cambricon Technol Co Ltd Beijing Peoples R China Chinese Acad Sci Inst Comp Technol Intelligence Processor Res Ctr Beijing Peoples R China Chinese Acad Sci Inst Comp Technol State Key Lab Comp Architecture Beijing Peoples R China Chinese Acad Sci Inst Software Beijing Peoples R China CAS Ctr Excellence Brain Sci Beijing Peoples R China Michigan State Univ E Lansing MI 48824 USA

ISBN: (纸本)9781538662403

Neural networks have become the dominant algorithms rapidly as they achieve state-of-the-art performance in a broad range of applications such as image recognition, speech recognition and natural language processing. However, neural networks keep moving towards deeper and larger architectures, posing a great challenge to the huge amount of data and computations. Although sparsity has emerged as an effective solution for reducing the intensity of computation and memory accesses directly, irregularity caused by sparsity (including sparse synapses and neurons) prevents accelerators from completely leveraging the benefits;it also introduces costly indexing module in accelerators. In this paper, we propose a cooperative software/hardware approach to address the irregularity of sparse neural networks efficiently. Initially, we observe the local convergence, namely larger weights tend to gather into small clusters during training. Based on that key observation, we propose a software-based coarse-grained pruning technique to reduce the irregularity of sparse synapses drastically. The coarse-grained pruning technique, together with local quantization, significantly reduces the size of indexes and improves the network compression ratio. We further design a hardware accelerator, Cambricon-S, to address the remaining irregularity of sparse synapses and neurons efficiently. The novel accelerator features a selector module to filter unnecessary synapses and neurons. Compared with a state-of-the-art sparse neural network accelerator, our accelerator is 1.71x and 1.37x better in terms of performance and energy efficiency, respectively.

关键词： Synapses Neurons image coding Quantization (signal) Convergence Biological neural networks

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Performance Analysis of Multifarious Programmable Gate Array Architecture for Vedic Multiplier

Performance Analysis of Multifarious Programmable Gate Array...

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International conference on Computing Communication Control and Automation (ICCUBEA)

作者： Jitendra S. Edle Prashant R. Deshmukh Department of Electronics and Telecommunication Engineering Sipna college of Engineering & Technology Amravati India Department of Computer Science & Engineering Sipna college of Engineering & Technology Amravati India

Momentous signal processing elements have been designed and developed using modern integration technologies. Higher frequency of data execution with lowest power utilization in highly optimized area are the primal antithetic expectancy of the modern applications from recent technology. In order to achieve such distinguished peculiarities, in many real-time processing applications, higher throughput arithmetic operations are important. Multiplication is historic arithmetic operations in such applications. With the revolutionary developments in the field of Programmable architectures and Integration Technology, several FPGA devices are now a days available for prototyping. Through this creative writing, a detailed comparative study of the different Field Programmable Gate Arrays of Actel, Altera, Lattice, QuickLogic and Xilinx and have been conducted and presented the analytical outcome of the study, particularly for 32-bit Vedic Multiplier Architecture, implemented using concurrent Hardware Description Language. It is strongly essential to have cogent analysis of the FPGA performances which will be helpful to the numerous small and medium scale industry owners and first generation industrialists who are much inclined to stand in the market.

关键词： Field programmable gate arrays Computer architecture Lattices Logic gates Hardware design languages Programmable logic arrays

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低成本可重新架构色彩内插影像处理器积体电路架构设计

低成本可重新架构色彩内插影像处理器积体电路架构设计

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作者：赵文瑄中原大学

学位级别：硕士

本论文提出低成本的色彩补偿演算法，可实现于即时性色彩内插影像处理积体电路设计，在演算法部分以低成本、高品质为设计基础，演算法中包含的滤波器技术，分别为空间锐化滤波器与拉普拉斯滤波器的技术，可减少边缘像素点资讯的不足，... 详细信息

本论文提出低成本的色彩补偿演算法，可实现于即时性色彩内插影像处理积体电路设计，在演算法部分以低成本、高品质为设计基础，演算法中包含的滤波器技术，分别为空间锐化滤波器与拉普拉斯滤波器的技术，可减少边缘像素点资讯的不足，增强模糊的细节，提高影像还原品质，在设计上以低复杂度为基础，系数方面以2的倍数来运算，如此一来，在硬体部分，可使用位移器取代乘法器，大幅地降低电路成本，并搭配两条线缓冲记忆体，让影像处理器电路可以顺利处理像素点资讯，而不遗失所需运算之像素点资讯。本论文将参考文献[1]的主要运算电路，使用电路硬体共用技术，此项技术可以大大地降低硬体成本，提升逻辑使用率，并共用加法、减法与位移器提升逻辑使用率，共用加法、减法、位移器。电路设计完成后，先以FPGA验证电路功能是否正确，先以FPGA验证电路功能正确以后，再经过design Compiler合成电路经过design Compiler合成电路，最后使用IC Compiler光罩布局绕线进行晶片实现再使用IC Compiler光罩布局绕线，实现晶片。本论文之演算法，沿用先前参考文献[1]，在影像评估公式维持影像品质，而在硬体部份，工作频率可到达200MHz，逻辑闸数目为2.58K，在台积电0.18μm的CMOS制程下在0.18um的CMOS制程下，布局面积为32.2k μum2，相较于先前参考文献，本论文有效地降低11%之逻辑闸数目。

关键词：色彩滤波阵列色彩补偿色彩内插去马赛克空间锐化滤波拉普拉斯滤波

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4.9 A 1ms high-speed vision chip with 3D-stacked 140GOPS column-parallel PEs for spatio-temporal image processing

4.9 A 1ms high-speed vision chip with 3D-stacked 140GOPS col...

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IEEE International conference on Solid-State Circuits (ISSCC)

作者： Tomohiro Yamazaki Hironobu Katayama Shuji Uehara Atsushi Nose Masatsugu Kobayashi Sayaka Shida Masaki Odahara Kenichi Takamiya Yasuaki Hisamatsu Shizunori Matsumoto Leo Miyashita Yoshihiro Watanabe Takashi Izawa Yoshinori Muramatsu Masatoshi Ishikawa Sony Semiconductor Solutions Atsugi Japan Sony LSI Design Atsugi Japan University of Tokyo Bunkyo Japan

ISBN: (纸本)9781509037599

High-speed vision systems that combine high-frame-rate imaging and highly parallel signal processing enable instantaneous visual feedback to rapidly control machines over human-visual-recognition speeds. Such systems also enable a reduction in circuit scale by using a fast and simple algorithm optimized for high-frame-rate processing [1]. Previous studies on vision systems and chips [1-4] have yielded low imaging performance due to large matrix-based processing element (PE) parallelization [1-3], and low functionality of the limited-purpose column-parallel PE architecture [4], constraining vision-chip applications.

关键词： image color analysis Robot sensing systems Machine vision Imaging Object detection

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Classification accuracy improvement for neuromorphic computing systems with one-level precision synapses

Classification accuracy improvement for neuromorphic computi...

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Asia and South Pacific design Automation conference

作者： Yandan Wang Wei Wen Linghao Song Hai Helen Li Dept. of Electrical & Computer Engineering University of Pittsburgh Pittsburgh PA USA University of Pittsburgh Pittsburgh PA US

ISBN: (纸本)9781509015597

Brain inspired neuromorphic computing has demonstrated remarkable advantages over traditional von Neumann architecture for its high energy efficiency and parallel data processing. However, the limited resolution of synaptic weights degrades system accuracy and thus impedes the use of neuromorphic systems. In this work, we propose three orthogonal methods to learn synapses with one-level precision, namely, distribution-aware quantization, quantization regularization and bias tuning, to make image classification accuracy comparable to the state-of-the-art. Experiments on both multi-layer perception and convolutional neural networks show that the accuracy drop can be well controlled within 0.19% (5.53%) for MNIST (CIFAR-10) database, compared to an ideal system without quantization.

关键词： Quantization (signal) Memristors Biological neural networks Neurons Neuromorphics Tuning Training

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ROIC design for a 10k Pixel Photoresistive image Sensor with On-Chip Calibration 1

ROIC Design for a 10k Pixel Photoresistive Image Sensor with...

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1st New Generation of CAS conference (NGCAS )

作者： Ozmen, Cagatay Dirican, Aydin Hieu Nguyen Margala, Martin Univ Massachusetts Elect & Comp Engn Lowell MA 01854 USA

ISBN: (纸本)9781509064472

This paper describes a novel readout integrated circuit (ROIC) for a photoresistive image sensor array incorporating Wheatstone bridge configuration with a variable-gain switched-capacitor amplifier. A 12-bit R-2R ladder digital-to analog converter (DAC) and a variable-gain switched capacitor amplifier are used for on-chip offset and gain calibration. The bias voltage of the bridge is supplied by an on-chip DAC and made programmable between 0 to 1.8 Volts for ROIC performance optimization. This image sensor and ROIC system is intended to be used as an endoscope camera which demands strict silicon area and low power consumption requirements. A sample 1x16 line sensor is used for proof of concept. The ROIC is designed for the target of 30 frames per second output data rate for a 100x100 sensor. This work focuses on the analog signal processing chain of the ROIC. The nominal (base) resistance of each detector is assumed to have a variation of (+/- 10%). The proposed ROIC is designed in 0.18 mu m CMOS process. Effectiveness of the calibration method is demonstrated with post-layout simulations performed on 6 PVT corners.

关键词： Calibration Bridge circuits Detectors image sensors Capacitors Logic gates Switches

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Parcel delineation in agricultural lands

Parcel delineation in agricultural lands

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IEEE signal processing and Communications Applications (SIU)

作者： Hulya Yalcin Elektronik ve Haberleşme Mühendisliği Bölümü İstanbul Teknik Üniversitesi

ISBN: (纸本)9781509064953

Despite the increased agricultural fields and food production, advances in agricultural technology and know-how have also caused significant environmental change in many regions. Monitoring irrigated lands and updating information about the use of each agricultural parcel is very valuable for a variety of agricultural-related agencies for research purposes. Additionally, many applications such as updating cadastral information, land-cover or land-use mapping, estimating agricultural subsidies require primarily a parcel-based study. Hence, a correct delineation of the parcels becomes very crucial. In this paper, we propose an algorithm for automatic delineation of agricultural parcels. We first apply watershed segmentation to high resolution remote sensing imagery. Applying watershed segmentation yields many superpixels which do not correspond to the actual parcels in the scene. We assume that the geometric and texture properties of parcels to be segmented are different from each other, but they are similar for the superpixels that fall into the same parcel. In order to improve segmentation, the superpixels are merged based on the assumptions that superpixels that have similar textural characteristics and which are also within close proximity of each other should be merged. In order to evaluate the performance of the proposed method, percentage of correctly segmented parcel areas are computed with respect to the manual ground truth delineation.

关键词： Remote sensing image segmentation Agriculture Computers Nanoelectromechanical systems Multiresolution analysis Algorithm design and analysis

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Sensitivity Improvement of a Photoresistive image Sensor with Novel Programmable Dual Element Readout and Calibration Method 60

Sensitivity Improvement of a Photoresistive Image Sensor wit...

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60th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)

作者： Ozmen, Cagatay Dirican, Aydin Nguyen, Hieu Margala, Martin Univ Massachusetts Lowell Elect & Comp Engn Lowell MA 01854 USA

ISBN: (纸本)9781509063895

This paper describes a novel readout integrated circuit (ROIC) for a nanoscale photoresistive image sensor array with a novel dual element readout and calibration method. The dual element readout increases detector signal sensitivity and sensor dynamic range. It works on the assumption that adjacent nanoscale detectors have similar illumination levels. A novel on-chip two-point calibration method is also proposed;two on-chip 12-bit R-2R ladder digital-to-analog converters (DAC) are used for offset calibration, whereas the variable-gain switched-capacitor amplifier enables the gain calibration. The programmability feature allows the system to be converted to single element readout. Detector bias voltage is supplied by the two on-chip DACs and is programmable between 0 to 1.8 V for ROIC performance optimization. This image sensor and ROIC system is intended to be used as an endoscope camera which demands strict silicon area and low power consumption requirements. A sample 1x16 line sensor is used for proof of concept. This work focuses on the analog signal processing chain of the ROIC. The column-wise design makes the ROIC scalable for larger image sensor sizes. The proposed ROIC is designed in 0.18 mu m CMOS process and the system is verified with post-layout simulations.

关键词： Bridge circuits image sensors Detectors Calibration Capacitors Cameras Switches

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Performance Analysis of 1-Bit Full Adder using Different design Techniques

Performance Analysis of 1-Bit Full Adder using Different Des...

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IEEE International conference on Recent Trends in Electronics, Information & Communication Technology

作者： P. Sreelatha P Koti Lakshmi Rameshwar rao ME Student ECE Dept UCE Osmania University Hyderabad Asst. Professor Dept of ECE UCE Osmania University Hyderabad Adjunct professor Dept. of ECE UCE Osmania University Hyderabad

ISBN: (纸本)9781509037056

A fast and power-efficient full Adder plays key role in electronics trade especially performing arithmetic operations in microprocessors, digital signal processing (DSP) and image processing. Full Adder is such a significant element which contributes substantially to the total power consumption of the network. In this paper, 1-bit Full Adder has been designed which is then analyzed. The leakage power consumption has been done in the circuit using different technologies such as 120nm and *** designed circuit has shown a incredible reduction in the consumed power of 97.8% and an increase of 12.7% in consumed area compared to GDI full adder in 120nm foundry. By using DSCH2 and MICROWIND2 tools, the designed 1-bit complete adder are compared in phrases of leakage power consumption and surface area.

关键词： CMOS VLSI Full Adder Power consumption CMOS technology full adder Power consumption CMOS technology design techniques 1-bit

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