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检索条件"任意字段=2017 Conference on Design and Architectures for Signal and Image Processing, DASIP 2017"

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design and simulation of quadrature mirror filters-based channelization architecture for subband coding applications using FPGA

Design and simulation of quadrature mirror filters-based cha...

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IEEE International conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT)

作者： Kumar S Anil S L Gangadharaiah Lakshmi Shrinivasan RIT

ISBN: (纸本)9781509037056

Subband coding is a method in which the incoming digital signal is decomposed into its constituent low-pass and high-pass signal components. The decomposed components further down-sampled and encoded using lossy compression methods. The key application of subband coding is in speech compression, image compression etc. The subband coding method uses a set of filters called Quadrature Mirror Filters (QMF) which consists of a low-pass filter and its quadrature shift high-pass filter. Resource efficient design and reconfigurability are the key requirements of digital channelization architectures. This paper presents an architecture for realizing the 2-channel Quadrature Mirror Filter Analysis Bank on FPGA using three different multiplier structures namely Booth Multiplier, Baugh-Wooley Multiplier and Signed Vedic Multiplier. This paper also gives a brief comparison between different proposed structures in-terms of speed and area consumption. Simulations and synthesis are carried out using Xilinx ISE with Virtex-5 XC5VLX330T-2FF1738 FPGA device environment.

关键词： Filter banks Finite impulse response filters Low pass filters Computer architecture Field programmable gate arrays IIR filters

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Impact of interactivity on the assessment of quality of experience for light field content

Impact of interactivity on the assessment of quality of expe...

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International Workshop on Quality of Multimedia Experience, QoMEx

作者： Irene Viola Martin Řeřábek Touradj Ebrahimi EPFL Multimedia Signal Processing Group Lausanne Switzerland

The recent advances in light field imaging are changing the way in which visual content is captured, processed and consumed. Storage and delivery systems for light field images rely on efficient compression algorithms. Such algorithms must additionally take into account the feature-rich rendering for light field content. Therefore, a proper evaluation of visual quality is essential to design and improve coding solutions for light field content. Consequently, the design of subjective tests should also reflect the light field rendering process. This paper aims at presenting and comparing two methodologies to assess the quality of experience in light field imaging. The first methodology uses an interactive approach, allowing subjects to engage with the light field content when assessing it. The second, on the other hand, is completely passive to ensure all the subjects will have the same experience. Advantages and drawbacks of each approach are compared by relying on statistical analysis of results and conclusions are drawn. The obtained results provide useful insights for future design of evaluation techniques for light field content.

关键词： image coding Visualization Imaging image resolution image color analysis Software Temperature measurement

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Classification accuracy improvement for neuromorphic computing systems with one-level precision synapses

Classification accuracy improvement for neuromorphic computi...

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Asia and South Pacific design Automation conference

作者： Yandan Wang Wei Wen Linghao Song Hai Helen Li Dept. of Electrical & Computer Engineering University of Pittsburgh Pittsburgh PA USA University of Pittsburgh Pittsburgh PA US

ISBN: (纸本)9781509015597

Brain inspired neuromorphic computing has demonstrated remarkable advantages over traditional von Neumann architecture for its high energy efficiency and parallel data processing. However, the limited resolution of synaptic weights degrades system accuracy and thus impedes the use of neuromorphic systems. In this work, we propose three orthogonal methods to learn synapses with one-level precision, namely, distribution-aware quantization, quantization regularization and bias tuning, to make image classification accuracy comparable to the state-of-the-art. Experiments on both multi-layer perception and convolutional neural networks show that the accuracy drop can be well controlled within 0.19% (5.53%) for MNIST (CIFAR-10) database, compared to an ideal system without quantization.

关键词： Quantization (signal) Memristors Biological neural networks Neurons Neuromorphics Tuning Training

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Compressed sensing image reconstruction based on joint statistical and structural priors

Compressed sensing image reconstruction based on joint stati...

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International conference on Advanced Communication Technology (ICACT)

作者： Jiahui Li Shaohua Wu Huan Huang Jian Jiao Harbin Institute a/Technology Shenzhen Graduate School Shenzhen Guangdong China

ISBN: (纸本)9781509048922

Due to proper use of the image sparsity, CS (compressed sensing) image compression has made great achievements in the field of image compression without the constraint of Nyquist sampling law. A great deal of researches indicate that there exist obvious statistical and structural priors regularity for image information distribution, while traditional CS image compression algorithms only use the sparse characteristic of the image information. In this paper, we propose a CS image reconstruction algorithm based on the joint statistical and structural priors which can achieve efficient image reconstruction via a small amount of measurements. With the full use of inter-scale and intra-scale relations of the sparse coefficients, we optimize the iterative hard thresholding CS algorithm specifically by building a GSM model to constrain the local coefficients distribution statistically, and a tree model to constrain the global coefficients distribution structurally. Extensive simulations have been conducted and the results show that the proposed method has achieved a considerable promotion both on the speed and the PSNR gain of image reconstruction, compared with the traditional recovery algorithms under the same compression ratio.

关键词： image reconstruction image coding Algorithm design and analysis signal processing algorithms Matching pursuit algorithms Wavelet coefficients GSM

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ROIC design for a 10k Pixel Photoresistive image Sensor with On-Chip Calibration 1

ROIC Design for a 10k Pixel Photoresistive Image Sensor with...

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1st New Generation of CAS conference (NGCAS )

作者： Ozmen, Cagatay Dirican, Aydin Hieu Nguyen Margala, Martin Univ Massachusetts Elect & Comp Engn Lowell MA 01854 USA

ISBN: (纸本)9781509064472

This paper describes a novel readout integrated circuit (ROIC) for a photoresistive image sensor array incorporating Wheatstone bridge configuration with a variable-gain switched-capacitor amplifier. A 12-bit R-2R ladder digital-to analog converter (DAC) and a variable-gain switched capacitor amplifier are used for on-chip offset and gain calibration. The bias voltage of the bridge is supplied by an on-chip DAC and made programmable between 0 to 1.8 Volts for ROIC performance optimization. This image sensor and ROIC system is intended to be used as an endoscope camera which demands strict silicon area and low power consumption requirements. A sample 1x16 line sensor is used for proof of concept. The ROIC is designed for the target of 30 frames per second output data rate for a 100x100 sensor. This work focuses on the analog signal processing chain of the ROIC. The nominal (base) resistance of each detector is assumed to have a variation of (+/- 10%). The proposed ROIC is designed in 0.18 mu m CMOS process. Effectiveness of the calibration method is demonstrated with post-layout simulations performed on 6 PVT corners.

关键词： Calibration Bridge circuits Detectors image sensors Capacitors Logic gates Switches

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Research on image amplitude acquisition and denoising based on wireless charging positioning system

Research on image amplitude acquisition and denoising based ...

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IEEE conference on Energy Internet and Energy System Integration (EI2)

作者： Pingjuan Niu Yukai Sun Yunlei Guo Lei Liu School of Electronics and Information Engineering Tianjin Polytechnic University Tianjin China School of Electrical Engineering and Automation Tianjin Polytechnic University Tianjin China

ISBN: (纸本)9781538614280

Located in wireless charging system, the receiver and the transmitter coil accurate alignment is a way to improve transmission efficiency. But the noise in the image acquisition interface will interfere with the acquisition of information, affecting the process of coil alignment in the process of extraction and identification. In this paper, the clustering analysis method is used to compute the set of data points, which is divided into noise set and effective point set by mapping of composite. The data set is orthogonally transformed, polarized, sparsely formed, easy to classify, and remove noise. Experiments show that the classification method has obvious effect, and the noise is removed correctly, and the peak signal to noise ratio is improved by 5% by improving the weight processing method. In this paper, the noise distribution characteristics are analyzed, the sparse expression is realized by orthogonal transform and the noise is removed by iterative mixed weighting.

关键词： Noise reduction Clustering algorithms Inductive charging Algorithm design and analysis Transforms image segmentation Classification algorithms

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Performance Analysis of Multifarious Programmable Gate Array Architecture for Vedic Multiplier

Performance Analysis of Multifarious Programmable Gate Array...

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International conference on Computing Communication Control and Automation (ICCUBEA)

作者： Jitendra S. Edle Prashant R. Deshmukh Department of Electronics and Telecommunication Engineering Sipna college of Engineering & Technology Amravati India Department of Computer Science & Engineering Sipna college of Engineering & Technology Amravati India

Momentous signal processing elements have been designed and developed using modern integration technologies. Higher frequency of data execution with lowest power utilization in highly optimized area are the primal antithetic expectancy of the modern applications from recent technology. In order to achieve such distinguished peculiarities, in many real-time processing applications, higher throughput arithmetic operations are important. Multiplication is historic arithmetic operations in such applications. With the revolutionary developments in the field of Programmable architectures and Integration Technology, several FPGA devices are now a days available for prototyping. Through this creative writing, a detailed comparative study of the different Field Programmable Gate Arrays of Actel, Altera, Lattice, QuickLogic and Xilinx and have been conducted and presented the analytical outcome of the study, particularly for 32-bit Vedic Multiplier Architecture, implemented using concurrent Hardware Description Language. It is strongly essential to have cogent analysis of the FPGA performances which will be helpful to the numerous small and medium scale industry owners and first generation industrialists who are much inclined to stand in the market.

关键词： Field programmable gate arrays Computer architecture Lattices Logic gates Hardware design languages Programmable logic arrays

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Performance Analysis of 1-Bit Full Adder using Different design Techniques

Performance Analysis of 1-Bit Full Adder using Different Des...

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IEEE International conference on Recent Trends in Electronics, Information & Communication Technology

作者： P. Sreelatha P Koti Lakshmi Rameshwar rao ME Student ECE Dept UCE Osmania University Hyderabad Asst. Professor Dept of ECE UCE Osmania University Hyderabad Adjunct professor Dept. of ECE UCE Osmania University Hyderabad

ISBN: (纸本)9781509037056

A fast and power-efficient full Adder plays key role in electronics trade especially performing arithmetic operations in microprocessors, digital signal processing (DSP) and image processing. Full Adder is such a significant element which contributes substantially to the total power consumption of the network. In this paper, 1-bit Full Adder has been designed which is then analyzed. The leakage power consumption has been done in the circuit using different technologies such as 120nm and *** designed circuit has shown a incredible reduction in the consumed power of 97.8% and an increase of 12.7% in consumed area compared to GDI full adder in 120nm foundry. By using DSCH2 and MICROWIND2 tools, the designed 1-bit complete adder are compared in phrases of leakage power consumption and surface area.

关键词： CMOS VLSI Full Adder Power consumption CMOS technology full adder Power consumption CMOS technology design techniques 1-bit

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Sensitivity Improvement of a Photoresistive image Sensor with Novel Programmable Dual Element Readout and Calibration Method 60

Sensitivity Improvement of a Photoresistive Image Sensor wit...

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60th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)

作者： Ozmen, Cagatay Dirican, Aydin Nguyen, Hieu Margala, Martin Univ Massachusetts Lowell Elect & Comp Engn Lowell MA 01854 USA

ISBN: (纸本)9781509063895

This paper describes a novel readout integrated circuit (ROIC) for a nanoscale photoresistive image sensor array with a novel dual element readout and calibration method. The dual element readout increases detector signal sensitivity and sensor dynamic range. It works on the assumption that adjacent nanoscale detectors have similar illumination levels. A novel on-chip two-point calibration method is also proposed;two on-chip 12-bit R-2R ladder digital-to-analog converters (DAC) are used for offset calibration, whereas the variable-gain switched-capacitor amplifier enables the gain calibration. The programmability feature allows the system to be converted to single element readout. Detector bias voltage is supplied by the two on-chip DACs and is programmable between 0 to 1.8 V for ROIC performance optimization. This image sensor and ROIC system is intended to be used as an endoscope camera which demands strict silicon area and low power consumption requirements. A sample 1x16 line sensor is used for proof of concept. This work focuses on the analog signal processing chain of the ROIC. The column-wise design makes the ROIC scalable for larger image sensor sizes. The proposed ROIC is designed in 0.18 mu m CMOS process and the system is verified with post-layout simulations.

关键词： Bridge circuits image sensors Detectors Calibration Capacitors Cameras Switches

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4.6 A 1/2.3inch 20Mpixel 3-layer stacked CMOS image Sensor with DRAM

4.6 A 1/2.3inch 20Mpixel 3-layer stacked CMOS Image Sensor w...

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IEEE International conference on Solid-State Circuits (ISSCC)

作者： Tsutomu Haruta Tsutomu Nakajima Jun Hashizume Taku Umebayashi Hiroshi Takahashi Kazuo Taniguchi Masami Kuroda Hiroshi Sumihiro Koji Enoki Takatsugu Yamasaki Katsuya Ikezawa Atsushi Kitahara Masao Zen Masafumi Oyama Hiroki Koga Hidenobu Tsugawa Tomoharu Ogita Takashi Nagano Satoshi Takano Tetsuo Nomoto Sony Semiconductor Solutions Atsugi Japan Sony Semiconductor Manufacturing Atsugi Japan Sony LSI Design Atsugi Japan

ISBN: (纸本)9781509037599

In recent years, the performance of cellphone cameras has improved, and is becoming comparable to that of SLR cameras. However, the big difference between cellphone cameras and SLR cameras is the distortion due to the rolling exposure of CMOS image sensors (CISs) because cellphone cameras cannot have a mechanical shutters [1]. In addition to this technical problem, the demands for high quality in dark situations and for movies are increasing. Frame-level signal processing can solve these problems, but previous generations of CIS could not achieve both high-speed readout and accessible I/F speed. This paper presents 3-layer-stacked back-illuminated CMOS image Sensor (3L-BI-CIS) with mounted DRAM as the frame memory.

关键词： Random access memory Motion pictures CMOS image sensors Cameras Distortion

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