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检索条件"任意字段=2017 Conference on Design and Architectures for Signal and Image Processing, DASIP 2017"

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design and hardware implementation of a low-complexity multiuser vector precoder

Design and hardware implementation of a low-complexity multi...

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2010 conference on design and architectures for signal and image processing, dasip2010

作者： Barrenechea, Maitane Barbero, Luis Mendicute, Mikel Thompson, John University of Mondragón Department of Electronics and Computer Science Mondragón Spain Queen's University Belfast Institute of Electronics Communications and Information Technology Belfast United Kingdom University of Edinburgh Institute for Digital Communications Edinburgh United Kingdom

ISBN: (纸本)9781424487356

In the multiuser MIMO broadcast channel, the use of precoding techniques is required in order to detect the signal at the users' terminals without any cooperation between them. This contribution presents the design and hardware implementation of a high-capacity precoder based on vector perturbation. The most challenging part of the vector precoding (VP) scheme, that is, the search for the perturbing signal in an infinite lattice, has been completed by the reduced-complexity albeit high-performance Fixed Sphere Encoder (FSE) algorithm. The most remarkable feature of the FSE is its fixed complexity, which makes it highly suitable for hardware implementation on field-programmable gate arrays (FPGA), where the parallelization and pipelining of resources can be applied to enhance the system throughput. An optimized reduced-complexity implementation is proposed, which achieves high performance with a reduced hardware resource usage. © 2010 IEEE.

关键词： Field programmable gate arrays (FPGA)

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FPGA-based rectification of stereo images

FPGA-based rectification of stereo images

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2010 conference on design and architectures for signal and image processing, dasip2010

作者： Rodrigues, João G.P. Ferreiray, João Canas INESC Porto Faculdade de Engenharia Universidade do Porto Portugal IT - Instituto de Telecomunicações Portugal

ISBN: (纸本)9781424487356

In order to obtain depth information about a scene in computer vision, one needs to process pairs of stereo images. The calculation of dense depth maps in real-time is computationally challenging as it requires searching for matches between objects in both images. The task is significantly simplified if the images are rectified, a process which horizontally aligns the objects in both images. The process of stereo images rectification has several steps with different computational requirements. The steps include 2D searches for high fidelity matches, precise matrix calculations, and fast pixel coordinate transformations and interpolations. In this project, the complete process is effectively implemented in a Spartan-3 FPGA, taking advantage of a MicroBlaze soft core for slow but precise calculations, and of fast dedicated hardware support for achieving the real-time requirements. The implemented system successfully performs real-time rectification on the images from two video cameras, with a resolution of 640×480 pixels and a frame rate of 25 fps, and is easily configured for videos with higher resolutions. The experimental results show very good quality, with rectified images having a maximum vertical disparity of two pixels, thereby showing that stereo image rectification can be efficiently achieved in an low-resource FPGA (with 64KB for program instructions and data). © 2010 IEEE.

关键词： Stereo image processing

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Low power noise detection circuit utilizing switching activity measurement method

Low power noise detection circuit utilizing switching activi...

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2010 conference on design and architectures for signal and image processing, dasip2010

作者： Razak, Zulhakimi Erdogan, Ahmet Arslan, Tughrul System Level Integration Group School of Engineering University of Edinburgh United Kingdom

ISBN: (纸本)9781424487356

Noise often limits the performance of transmitted signals and degrades signals quality. Moreover, stochastic nature of noise makes it difficult to predict, and hence, is hard to detect. In hardware implementation, the reduction of noise can only be optimized in the baseband where complex and intensive computation is executed using digital signal processors (DSPs). Although analog pre-filtering is applied at receiver front-end to reduce interferences, fractions of noise still exist due to non-ideality of the device. We present a method to detect noise in signal using switching activity measurement (SWAM) of analog-to-digital converter (ADC) output. Simulation results show that switching activity of digital outputs varies with different signal-to-noise ratio (SNR) values where high SNR value leads to low switching activity. A noise detection unit (NDU) is implemented and is synthesized using AMS 0.35μm/3.3V CMOS standard library. The result shows minimum overhead where NDU occupies only 774 equivalent 2-input NAND gates and consumes only 978μW of power. With advantage of small complexity and power usage, NDU is attractive to be used in ADC-based systems and noise prone devices in order to detect noise and leads to further signal improvement. © 2010 IEEE.

关键词： signal to noise ratio

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GPU architecture evaluation for multispectral and hyperspectral image analysis

GPU architecture evaluation for multispectral and hyperspect...

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作者： Fresse, Virginie Houzet, Dominique Gravier, Christophe Hubert Curien Laboratory UMR CNRS 5516 Université de Lyon F-42023 Saint-Etienne France CNRS UMR 5516 Laboratoire Hubert Curien F-42000 Saint-Etienne France Université de Saint-Etienne Jean-Monnet F-42000 Saint-Etienne France GIPSA Lab Grenoble-INP 961 rue de la Houille Blanche 38 St-Martin d'Heres Grenoble France TELECOM Saint-Etienne SATIN Équipe Associée de l'Institut TELECOM DIOM EA3523 F-42023A Saint-Etienne France

ISBN: (纸本)9781424487356

Graphical processing Units (GPU) architectures are massively used for resource-intensive computation. Initially dedicated to imaging, vision and graphics, these architectures serve nowadays a wide range of multi-purpose applications. The GPU structure, however, does not suit all applications. This can lead to performance shortage. Among several applications, the aim of this work is to analyze GPU structures for image analysis applications in multispectral to ultraspectral imaging. Algorithms used for the experiments are multispectral and hyperspectral imaging dedicated to art authentication. Such algorithms use a high number of spatial and spectral data, along with both a high number of memory accesses and a need for high storage capacity. Timing performances are compared with CPU architecture and a global analysis is made according to the algorithms and GPU architecture. This paper shows that GPU architectures are suitable to complex image analysis algorithm in multispectral. © 2010 IEEE.

关键词： Graphics processing unit

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Exploration platform of embedded simd architecture for autonomous retinas

Exploration platform of embedded simd architecture for auton...

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conference on design and architectures for signal and image processing

作者： Stéphane Chevobbe Suresh Pajaniradja Laurent Letellier Embedded Computing Laboratory CEA/List Gif-sur-Yvette France

An integrated smart camera is a single chip composed of a sensor tightly coupled with one or more processing elements. The image processing applications that are mapped on such systems can require processing power in the range of supercomputer. To face the increasing application needs we propose in this paper a SIMD based processor optimized for the low and intermediate level of image processing. The architecture is composed of several SIMD cluster. Each cluster includes a configurable number of 2-Way PE (processing Element) ranging from 32 to 256 running at 200 MHz. These cluster configurations provide between 12 to 102 GOPS.

关键词： Pixel image processing Registers Hardware Computer architecture Parallel processing Software

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On-chip compression for HDR image sensors

On-chip compression for HDR image sensors

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conference on design and architectures for signal and image processing

作者： Fadoua Guezzi Messaoud Arnaud Peizerat Antoine Dupret Yves Blanchard L3I-MINATEC CEA-LETI Grenoble France ESYCOM ESIEE Paris Paris-Est University Noisy le Grand France

An image compressing technique for High Dynamic Range (HDR) image sensors is introduced. Compression is performed in two steps: Pixel value coding optimization followed by DCT-based (Discrete Cosine Transform) compression. A floating point coding technique is first used with a common exponent shared between pixels of the same block, and then a DCT is applied to each group of pixels. This new concept, while maintaining low complexity architecture, shows a compression ratio of 75 % and retains a good image quality with a PSNR of about 40 dB.

关键词： image coding Pixel PSNR Discrete cosine transforms Encoding image sensors image reconstruction

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architectures and signal reconstruction methods for nanosecond resolution Integrated Streak Camera in standard CMOS technology

Architectures and signal reconstruction methods for nanoseco...

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conference on design and architectures for signal and image processing

作者： Martin Zlatanski Wilfried Uhring Virginie Zint Jean-Pierre Le Normand Daniel Mathiot Institut d'Electronique du Solide et des Systèmes CNRS Université de Strasbourg Strasbourg France

This paper presents the state of the art of the Integrated Streak Camera (ISC) architectures in standard CMOS technology. It focuses on some of the methods required for reconstructing the luminous events profile from the chip raw data. Two main ISC architectures are presented. The first adopts the traditional for the most silicon imagers pixel array configuration, where the photocharges-induced signal is processed directly in-pixel. The second approach is based on a single light detecting vector, comparable to the slit of a Conventional Streak Camera (CSC), coupled to an amplifier stage and an analog sampling and storage unit. For both architectures, depending on the on-chip processing of the photocharges, appropriate signal reconstruction techniques are required in order to restore the luminous signal shape. A novel single vector ISC front-end architecture with an asynchronous photodiode reset scheme is presented. Algorithms allowing the luminous event reconstruction are proposed and validated through simulations for all the ISCs considered.

关键词： Pixel Photodiodes Optical sensors Cameras Optical imaging Delay image reconstruction

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High speed Fp multipliers and adders on FPGA platform

High speed Fp multipliers and adders on FPGA platform

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conference on design and architectures for signal and image processing

作者： Santosh Ghosh Debdeep Mukhopadhyay Dipanwita Roy Chowdhury Department of Computer Science & Engineering Indian Institute of Technology Kharagpur West Bengal India Department of Computer Science & Engineering Indian Institute of Technology Kharagpur Kharagpur West Bengal India

The paper proposes high speed FPGA implementations of adders and multipliers in F p . The work shows through experimental results that due to optimized addition chain available in such devices, Karatsuba decomposition upto a particular level improves the performance. Further the paper modifies existing interleaved multiplier using Montgomery ladder and the high speed adder circuits. Extensive experiments have been performed. The result shows that the proposed design provides 70% speedup from the best known designs.

关键词： Adders Field programmable gate arrays Algorithm design and analysis Performance evaluation Computer architecture Elliptic curves Registers

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An FPGA softcore based implementation of a bird call recognition system for sensor networks

An FPGA softcore based implementation of a bird call recogni...

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conference on design and architectures for signal and image processing

作者： Hongzhi Liu Neil W. Bergmann School of ITEE University of Queensland Australia

To investigate the on-sensor processing capabilities of FPGAs, this paper presents a bird call recognition system based on linear predictive cepstral coefficients (LPCC) and dynamic time warping (DTW) algorithms for sensor network applications, and compares two different implementations on a Xilinx Spartan-3E FPGA with MicroBlaze soft processor. The experimental results show that compared to the software-only solution, the software / hardware (SW/HW) implementation with hardware coprocessor for DTW yields significant performance improvement by the factor of 13.8 and 33.4 respectively for two example inputs, and achieves about 31.1 times energy efficiency by using only 7.5% more power.

关键词： Field programmable gate arrays Hardware Software Birds Feature extraction Digital signal processing Energy efficiency

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Dual-core reconfigurable demosaicing engine for next generation of portable camera systems

Dual-core reconfigurable demosaicing engine for next generat...

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conference on design and architectures for signal and image processing

作者： Xin Zhao Ying Yi Ahmet T Erdogan Tughrul Arslan School of Engineering Kings Buildings University of Edinburgh Edinburgh UK

This paper presents a high performance dual-core reconfigurable processor implementation methodology for a demosaicing system that targets next generation camera systems. The implementation methodology is based on dual-core architecture with coarse-grained dynamically reconfigurable processors. The demosaicing system adopts Freeman's algorithm that has been partitioned and mapped onto two customized and tailored heterogeneous processor cores. The demosaicing engine's implementation has been optimized by compilation techniques and special approaches for the targeting processor. Simulation results demonstrate that the resulting demosaicing system provides high throughput reaches up to 241.6Mpixels/s, which represents a 1.82x speedup compared to a single-core implementation.

关键词： image color analysis Pixel Pipeline processing Kernel Filtering Multicore processing

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