检索结果-内蒙古大学图书馆

conference on design and architectures for signal & image processing

作者： Sarjanoja, Sampsa Boutellier, Jani Hannuksela, Jari Univ Oulu Ctr Machine Vis Res Oulu Finland

ISBN: (纸本)9791092279115

Noise reduction is often performed at an early stage of the image processing path. In order to keep the processing delays small in different computing platforms, it is important that the noise reduction is performed swiftly. In this paper, the block-matching and three-dimensional filtering (BM3D) denoising algorithm is implemented on heterogeneous computing platforms using OpenCL and CUDA frameworks. To our knowledge, these implementations are the first successful open source attempts to use GPU computation for BM3D denoising. The presented GPU implementations are up to 7.5 times faster than their respective CPU implementations. At the same time, the experiments illustrate general design challenges in using massively parallel processing platforms for the calculation of complex imaging algorithms.

关键词： image denoising Parallel processing Parallel algorithms Mobile computing

来源：评论

学校读者我要写书评

暂无评论

A 3D reconstruction from real-time stereoscopic images using GPU

A 3D reconstruction from real-time stereoscopic images using...

引用

2013 7th conference on design and architectures for signal and image processing, dasip 2013

作者： Gomez-Balderas, J.E. Houzet, D. Grenoble Image Parole Signal Automatique Lab. GIPSA-Lab UMR5216 Grenoble France

ISBN: (纸本)9791092279016

In this article we propose a new technique to obtain a three-dimensional (3D) reconstruction from stereoscopic images taken by a stereoscopic system in real-time. To parallelize the 3D reconstruction we propose a method that uses a Graphics Processors Unit (GPU) and a disparity map from block matching algorithm (BM). The results obtained permit us to accelerate the images processing time, measured in frames per second (FPS) with respect to the same method using a Central processing Unit (CPU). The advantage of speed using GPU advocates our system for practical applications such as aerial reconnaissance, cartography, robotic navigation and obstacle detection.

关键词： Graphics processing unit

来源：评论

学校读者我要写书评

暂无评论

A Scalable Hardware Architecture for Retinal Blood Vessel Detection in High Resolution Fundus images 8

A Scalable Hardware Architecture for Retinal Blood Vessel De...

引用

8th conference on design and architectures for signal and image processing (dasip)

作者： Bendaoudi, Hamza Cheriet, Farida Ben Tahar, Houssem Langlois, J. M. Pierre Polytech Montreal Dept Comp & Software Engn Montreal PQ Canada Diagnos Inc Brossard PQ Canada

ISBN: (纸本)9791092279061

Blood vessel detection from high resolution fundus images is a necessary step in several medical applications. Automatic blood vessels detection is a computing intensive task which raises the need for accelerated hardware architectures. In this paper, we propose a scalable hardware architecture for blood vessel detection using a matched filter (MF). The algorithm is made hardware friendly using parallel processing and efficient resources sharing to achieve real-time performances. The paper also introduces a tool for the automatic generation of an HDL description based on the proposed architecture as a template. The tool takes as input the parameters of the filter to deal with the parameter selection problem and to make their choice more flexible. Performances in terms of area utilization and maximum frequency are reported. Several designs were verified and implemented on an FPGA platform. The results show significant improvements over the state of the art implementations, up to a factor of 10x for high resolution fundus images.

关键词： Retinal blood vessels detection Hardware acceleration Scalable hardware architectures

来源：评论

学校读者我要写书评

暂无评论

Flexible VLIW processor based on FPGA for real-time image processing

Flexible VLIW processor based on FPGA for real-time image pr...

引用

2011 conference on design and architectures for signal and image processing, dasip 2011

作者： Brost, Vincent Meunier, Charles Saptono, Debyo Yang, Fan LE2I-CNRS 5158 Laboratory University of Burgundy 21078 Dijon France

ISBN: (纸本)9781457706196

Modern FPGA chips, with their larger memory capacity and reconfigurability potential, are opening new frontiers in rapid prototyping of embedded systems. With the advent of high density FPGAs it is now possible to implement a high performance Very Long Instruction Word (VLIW) processor core in an FPGA. With VLIW architecture, the processor effectiveness depends on the ability of compilers to provide sufficient Instruction Level Parallelism (ILP) from program code. This paper describes research result about enabling the VLIW processor model for real-time processing applications by exploiting FPGA technology. Our goals are to keep the flexibility of processors in order to shorten the development cycle, and to use the powerful FPGA resources in order to increase real-time performance. We present a flexible VLIW VHDL processor model with a variable instruction set and a customizable architecture which allow exploiting intrinsic parallelism of a target application using advanced compiler technology and implementing it in an optimal manner on FPGA. Some common algorithms of image processing were tested and validated on an FPGA Virtex-6 based board using the proposed development cycle. Our approach applies some criteria for co-design tools: flexibility, modularity, performance, and reusability. © 2011 IEEE.

关键词： Field programmable gate arrays (FPGA)

来源：评论

学校读者我要写书评

暂无评论

Custom Processor design for Efficient, yet Flexible Lucas-Kanade Optical Flow

Custom Processor Design for Efficient, yet Flexible Lucas-Ka...

引用

conference on design and architectures for signal and image processing (dasip)

作者： Smets, Sander Goedeme, Toon Verhelst, Marian Katholieke Univ Leuven MICAS ESAT Leuven Belgium Katholieke Univ Leuven PSI EAVISE Campus De Nayer St Katelijne Waver Belgium

ISBN: (纸本)9791092279153

State-of-the-art solutions to optical flow fail to jointly offer high density flow estimation, low power consumption and real time operation, rendering them unsuitable for embedded applications. Joint hardware-software scalability at run-time is crucial to achieve these conflicting requirements in one device. This paper therefore presents a scalable Lucas-Kanade optical flow algorithm, together with a flexible power-optimized processor architecture. The C-programmable processor exploits algorithmic scalability through innovations in its memory structure, memory interface, and datapath optimized for efficient convolutions. Jointly, the scalable flow algorithm and optimized computer vision hardware platform enable applications to on-the-fly trade-off throughput and power consumption in function of flow density and accuracy. The processor chip is synthesized in 40nm CMOS technology and verified on FPGA. The architecture is capable of scaling the frame rate at run-time and processes 16fps of dense optical flow at 640x480 resolution with 15.06 degrees average angular error, while only consuming 24mW.

关键词： Machine vision programmable circuits parallel architectures real time systems low-power electronics

来源：评论

学校读者我要写书评

暂无评论

Energy and Execution Time Comparison of Optical Flow Algorithms on SIMD and GPU architectures 12

Energy and Execution Time Comparison of Optical Flow Algorit...

引用

12th conference on design and architectures for signal and image processing (dasip)

作者： Petreto, Andrea Hennequin, Arthur Koehler, Thomas Romera, Thomas Fargeix, Yohan Gaillard, Boris Bouyer, Manuel Meunier, Quentin L. Lacassagne, Lionel Sorbonne Univ CNRS LIP6 F-75005 Paris France Lheritier Alcen F-95862 Cergy Pontoise France

ISBN: (纸本)9781538682371

This article presents and compares optimized implementations of two optical flow algorithms on several target boards comprising multi-core SIMD processors and GPUs. The two algorithms are Horn-Schunck (HS) and TV-L1, and have been chosen because they are both well-known, and because of their different computational complexity and accuracy. For both algorithms, we have made parallel optimized SIMD implementations, while HS has also been implemented on GPUs. For each algorithm, the comparison between the different versions and target boards is carried out in a two-dimensional fashion: in terms of computing speed-in order to achieve real-time computation-and in terms of energy consumption since we target embedded systems. The results show that for HS, the GPUs are the most efficient in both dimensions, able to process in realtime performances (25 frames per second) up to 8Mpix images for 0.35J per image, against 1.8Mpix images for 0.24J per image on CPU. The results also highlight the impact of optimizations on TV-L1: far slower than HS without optimization, it can almost match its performance after optimization on CPU, and can achieve real-time performances with 0.25J for 1.4Mpix images. We hope these results will help developers design optical flow embedded systems.

关键词： Optimization Graphics processing units Optical imaging Computer architecture Real-time systems Embedded systems Power demand

来源：评论

学校读者我要写书评

暂无评论

HLS-based fast design space exploration of ad hoc hardware accelerators: A key tool for MPSoC synthesis on FPGA

HLS-based fast design space exploration of ad hoc hardware a...

引用

6th Annual conference on design and architectures for signal and image processing, dasip 2012

作者： Corre, Youenn Hoang, Van-Trinh Diguet, Jean-Philippe Heller, Dominique Lagadec, Loic Lab-STICC Université de Bretagne Sud 56100 Lorient France Lab-STICC Université de Bretagne Occidentale 29200 Brest France

ISBN: (纸本)9782953998726

Over the last decade many academic and industrial system synthesis and codesign tools have been proposed to designers. However most of these tools are based on IP Libraries but either these libraries are incomplete or are simply not adapted to the targets and constraints. It means that something important is missing when it comes to real implementations. We address this question in this paper and propose a flexible, fast and practical solution. We use high level synthesis (HLS) to obtain fast estimations of hardware accelerators that can then be embedded within the loop of a larger design space exploration flow. Once some solutions are selected they can be directly reuse to synthesise and produce real IPs. In this paper we present the approach and the tool as a key component of our heterogeneous multiprocessor synthesis framework. © 2012 ECSI.

关键词： High level synthesis

来源：评论

学校读者我要写书评

暂无评论

Hardware Acceleration of Maximum-Likelihood Angle Estimation for Automotive MIMO Radars

Hardware Acceleration of Maximum-Likelihood Angle Estimation...

引用

conference on design and architectures for signal and image processing (dasip)

作者： Meinl, Frank Kunert, Martin Blume, Holger Robert Bosch GmbH Adv Engn Sensor Syst Leonberg Germany Leibniz Univ Hannover Inst Mikroelekt Syst Hannover Germany

ISBN: (纸本)9791092279153

Direction of arrival (DOA) estimation is an important array signal processing technique, used by various applications such as radar, sonar or wireless communication. Most of the known DOA algorithms suffer from a significant performance reduction and even fail completely under difficult conditions, like small antenna aperture size, correlated signals or a small number of snapshots. Maximum-Likelihood (ML) methods have been investigated thoroughly and are known to still work even in such difficult scenarios. Though, the major drawback of ML methods is their computational cost, especially in the case of large MIMO (multiple-input multiple-output) configurations. This work presents a novel hardware accelerator architecture, which is able to compute the exact ML estimation in the case of one or two targets. It is shown, that the computational demanding vector product can be implemented with the help of CORDIC units, which help to save a considerable amount of hardware resources. Furthermore, the result of the single target estimator can be reused to efficiently compute the estimates in the two-target case. Finally, the performance of the architecture is evaluated by a FPGA implementation which is able to process more than 20 000 detections from 16 channels with 256 steering vectors in real-time (25 Hz).

关键词： Automotive radar driver assistance direction of arrival maximum-likelihood estimation radar signal processing CORDIC hardware accelerator FPGA

来源：评论

学校读者我要写书评

暂无评论

Special issue: design and architectures for real-time signal and image processing

引用

JOURNAL OF REAL-TIME image processing 2018年第1期15卷 1-2页

作者： Huebner, Michael Ruhr Univ Bochum ESIT Bochum Germany

The conference on design and architectures for signal and image processing-dasip addresses the development of complex applications involving signal, image and control processing based on a new approach called Algorithm–Architecture–Matching, which aims to leverage the design flow by a simultaneous study of both algorithmic and architectural issues, taking into account multiple design constraints, as well as algorithm and architecture optimizations. Embedded Systems and Cyber-physical Systems (CPS), especially in relation to image and signal processing, are a big step forward from the basic data-gathering networks, and they have been called to be the fourth industrial revolution. [...]the important contribution of CPS is its integration and connection of the hardware elements, e.g., sensors, actuators and computing units, with the software functionalities, e.g., automated routines and supervisor software, to perform energy efficiency and simultaneously keeping safety requirements. In the area of optimization, the paper “Parallel Light Speed Labeling: an efficient connected component algorithm for labeling and analysis on multi-core processors” [11] and “A linked list run-length-based single-pass connected component analysis for real-time embedded hardware” [12] are completing this excellent special issue.

关键词： ARCHITECTURE image processing Building construction time signal signals

来源：评论

学校读者我要写书评

暂无评论

Dataflow program analysis and refactoring techniques for design space exploration: MPEG-4 AVC/H.264 decoder implementation case study

Dataflow program analysis and refactoring techniques for des...

引用

2013 7th conference on design and architectures for signal and image processing, dasip 2013

作者： Ab Rahman, Ab Al-Hadi Casale Brunet, Simone Alberti, Claudio Mattavelli, Marco SCI-STI-MM École Polytechnique Fédérale de Lausanne Switzerland

ISBN: (纸本)9791092279016

This paper presents a methodology to perform design space exploration of complex signal processing systems implemented using the CAL dataflow language. In the course of space exploration, critical path in dataflow programs is first presented, and then analyzed using a new strategy for computational load reduction. These techniques, together with detecting design bottlenecks, point to the most efficient optimization directions in a complex network. Following these analysis, several new refactoring techniques are introduced and applied on the dataflow program in order to obtain feasible design points in the exploration space. For a MPEG-4 AVC/H.264 decoder software and hardware implementation, the multi-dimensional space can be explored effectively for throughput, resource, and frequency, with real-time decoding range from QCIF to HD resolutions.

关键词： Space research

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：