The proceedings contain 39 papers. The topics discussed include: research and design of multi sets of magnetic switches wound on one magnetic ring;redundant logic insertion and fault tolerance improvement in combinati...
ISBN:
(纸本)9781538603925
The proceedings contain 39 papers. The topics discussed include: research and design of multi sets of magnetic switches wound on one magnetic ring;redundant logic insertion and fault tolerance improvement in combinational circuits;simulation and modeling of charging and discharging of supercapacitors;mathematical estimation of logical masking capability of majority/minority gates used in nanoelectronic circuits;modeling and analysis of an uni-traveling carrier herterojucntion phototransistor;and a novel substitution box for encryption based on Lorenz equations.
Spectral radiation imaging diagnostic systems utilizing PDA (avalanche PhotoDiode Array) have been developed and deployed on the HFRC device (HUST Field Reversed Configuration Device). These systems are designed to me...
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A combined multi-pulse transmitting circuit for time domain electromagnetic detection is proposed in this paper. The dual-pulse energy boosting and high-voltage clamping technology are employed in transmitting system ...
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The demand for computation driven by machine learning and deep learning applications has experienced exponential growth over the past five years (Sevilla et al 2022 2022 international Joint conference on Neural Networ...
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The demand for computation driven by machine learning and deep learning applications has experienced exponential growth over the past five years (Sevilla et al 2022 2022 international Joint conference on Neural Networks (IJCNN) (IEEE) pp 1-8), leading to a significant surge in computing hardware products. Meanwhile, this rapid increase has exacerbated the memory wall bottleneck within mainstream Von Neumann architectures (Hennessy and Patterson et al 2011 Computer architecture: a quantitative approach (Elsevier)). For instance, NVIDIA graphical processing units (GPUs) have gained nearly a 200x increase in fp32 computing power, transitioning from P100 to H100 in the last five years (NVIDIA Tesla P100 2023 (***/en-us/data-center/tesla-p100/);NVIDIA H100 Tensor Core GPU 2023 (***/en-us/data-center/h100/)), accompanied by a mere 8x scaling in memory bandwidth. Addressing the need to mitigate data movement challenges, process-in-memory designs, especially resistive random-access memory (ReRAM)-based solutions, have emerged as compelling candidates (Verma et al 2019 IEEE Solid-State circuits Mag. 11 43-55;Sze et al 2017 Proc. IEEE 105 2295-329). However, this shift in hardware design poses distinct challenges at the design phase, given the limitations of existing hardware design tools. Popular design tools today can be used to characterize analog behavior via SPICE tools (PrimeSim HSPICE 2023 (***/implementation-and-signoff/ams-simulation/***)), system and logical behavior using Verilog tools (VCS 2023 (***/verification/simulation/***)), and mixed signal behavior through toolbox like CPPSIM (Meninger 2023 (***/Tutorials/wideband_fracn_***)). Nonetheless, the design of in-memory computing systems, especially those involving non-CMOS devices, presents a unique need for characterizing mixed-signal computing behavior across a large number of cells within a memory bank. This requirement f
In this paper, the implementation of a molecular diffusion model named Dynamic Lattice Liquid (DLL) is discussed. Two algorithms, sequential and parallel, implementing this model are examined. The presented theoretica...
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ISBN:
(纸本)9788363578190
In this paper, the implementation of a molecular diffusion model named Dynamic Lattice Liquid (DLL) is discussed. Two algorithms, sequential and parallel, implementing this model are examined. The presented theoretical considerations indicate sonic limitations of the sequential approach. The proposed parallel algorithm overcomes these limitations, hut it requires dedicated hardware to function. An example of such hardware, the FPGA-based HPC system named ARUZ, is presented.
Using CST simulation software, a sheet beam electron gun with U=33kV and I=0.68A was designed to meet the high-power requirements of the W-band sheet beam traveling-wave tube. The waist size of the elliptical sheet be...
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ARUZ (Analizator Rzeczywistych Ukladow Zlozonych, Analyser of Real Complex systems) is a massively parallel FPGA-based simulator located at BioNanoPark Lodz. This machine has been designed to reflect the Dynamic Latti...
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ISBN:
(纸本)9788363578190
ARUZ (Analizator Rzeczywistych Ukladow Zlozonych, Analyser of Real Complex systems) is a massively parallel FPGA-based simulator located at BioNanoPark Lodz. This machine has been designed to reflect the Dynamic Lattice Liquid (DLL) algorithm in hardware. In this paper, FPGA implementation details are presented for DLL functionality extension. This extension allows taking into account potential energy barriers in molecular simulations performed on ARUZ and thus modeling thermally-activated diffusion processes in liquids.
ARUZ (Analizator Rzeczywistych Ukladow Zlozonych, Analyser of Real Complex systems) is a massively parallel FPGA-based simulator located at. BioNanoPark Lodz. This machine has been designed to reflect the Dynamic Latt...
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ISBN:
(纸本)9788363578190
ARUZ (Analizator Rzeczywistych Ukladow Zlozonych, Analyser of Real Complex systems) is a massively parallel FPGA-based simulator located at. BioNanoPark Lodz. This machine has been designed to reflect the Dynamic Lattice Liquid (DLL) algorithm in hardware. In this paper, FPGA implementation details are presented for DLL functionality extension. This extension allows to simulate simple chemical reactions of first and second order realized in a parallel approach.
A design scheme of Duffing Chaotic circuit module is proposed based on Multisimin study. The operational amplifier is used to construct integrating circuit. The Duffing chaotic circuit is also designed based on the in...
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A Liquid Crystal on Silicon (LCoS) display system with resolution of 1280 ×1024 is designed and driven by FPGA (Field-Programmable Gate Array). The system uses DDR3 SDRAM (Double Data Rate3 Synchronous Dynamic Ra...
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