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Particle Mesh Ewald for Molecular Dynamics in OpenCL on an fpga Cluster

Particle Mesh Ewald for Molecular Dynamics in OpenCL on an F...

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Annual IEEE symposium on field-programmable Custom Computing Machines (FCCM)

作者： Lawrence C. Stewart Carlo Pascoe Emery Davis Brian W. Sherman Martin Herbordt Vipin Sachdeva Silicon Therapeutics Boston MA USA College of Engineering Boston University Boston MA USA

Molecular Dynamics (MD) simulations play a central role in physics-driven drug discovery. MD applications often use the Particle Mesh Ewald (PME) algorithm to accelerate electrostatic force computations, but efficient parallelization has proven difficult due to the high communication requirements of distributed 3D FFTs. In this paper, we present the design and implementation of a scalable PME algorithm that runs on a cluster of Intel Stratix 10 fpgas and can handle FFT sizes appropriate to address real-world drug discovery projects (grids up to 1283). To our knowledge, this is the first work to fully integrate all aspects of the PME algorithm (charge spreading, 3D FFT/IFFT, and force interpolation) within a distributed fpga framework. The design is fully implemented with OpenCL for flexibility and ease of development and uses 100 Gbps links for direct fpga-to-fpga communications without the need for host interaction. We present experimental data up to 4 fpgas (e.g., 206 microseconds per timestep for a 65536 atom simulation and 643 3D FFT), outperforming GPUs. Additionally, we discuss design scalability on clusters with differing topologies up to 64 fpgas (with expected performance greater than all known GPU implementations) and integration with other hardware components to form a complete molecular dynamics application. We predict best-case performance of 6.6 microseconds per timestep on 64 fpgas.

关键词： field programmable gate arrays

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Thread-Aware Area-Efficient High-Level Synthesis Compiler for Embedded Devices

Thread-Aware Area-Efficient High-Level Synthesis Compiler fo...

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international symposium on Code Generation and Optimization (CGO)

作者： Changsu Kim Shinnung Jeong Sungjun Cho Yongwoo Lee William Song Youngsok Kim Hanjun Kim POSTECH Pohang Republic of Korea Yonsei University Seoul Republic of Korea

ISBN: (数字)9781728186139

ISBN: (纸本)9781728186146

In the embedded device market, custom hardware platforms such as an application specific integrated circuit (ASIC) and a field programmable gate array (fpga) are attractive thanks to their high performance and power efficiency. However, its huge design costs make it challenging for manufacturers to timely launch new devices. High-level synthesis (HLS) helps significantly reduce the design costs by automating the translation of service algorithms into hardware logics; however, current HLS compilers do not fit well to embedded devices as they fail to produce area-efficient solutions while supporting concurrent events from diverse peripherals such as sensors, actuators and network modules. This paper proposes a new thread-aware HLS compiler named Duro that produces area-efficient embedded devices. Duro shares commonly-invoked functions and operators across different callers and threads with a new thread-aware area cost model, and thus effectively reduces the logic size. Moreover, Duro supports a variety of device peripherals by automatically integrating peripheral controllers and interfaces as peripheral drivers. The experiment results of six embedded devices with ten peripherals demonstrate that Duro reduces the area and energy dissipation of embedded devices by 28.5% and 25.3% compared with the designs generated by the state-of-the-art HLS compiler. This work also implements fpga prototypes of the six devices using Duro, and the measurement results show 65.3% energy saving over Raspberry Pi Zero with slightly better computation performance.

关键词： Performance evaluation Application specific integrated circuits Instruction sets Prototypes Hardware Sensors field programmable gate arrays

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On Feasibility of fpgas Without Dedicated programmable Interconnect Structure 19

On Feasibility of FPGAs Without Dedicated Programmable Inter...

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Proceedings of the 2019 acm/sigda international symposium on field-programmable gate arrays

作者： Anastasiia Kucherenko Stefan Nikolic Paolo Ienne École Polytechnique Fédérale de Lausanne (EPFL) Lausanne Switzerland

ISBN: (纸本)9781450361378

It is a well known fact that a great majority of fpga chip area goes into the programmable interconnect structure. Since area consumption is mostly proportional to the level of flexibility the interconnect structure offers, how much of this flexibility is really needed for the implementation of any design of interest is a logical question to pose. Going one step further, one may wonder if a dedicated programmable interconnect structure is even necessary. This work answers exactly this second question by providing constructive capability proofs, for a broad class of fpga architectures composed solely of look-up tables (LUTs) connected in a fixed manner, to implement any circuit graph. Our proposed architectures consist of identical cells of LUTs with fixed connections, arranged on a 2D grid. Direct wires between cell input and output pins are also allowed, enabling long uninterrupted connections. We begin by formalizing the above architecture class, and then describe an algorithm capable of mapping any circuit on one specific member of it, in which each cell consists of a single 4-LUT. We derive area and runtime bounds for the algorithm, and finally extend it to be applicable to any architecture in which no LUT receives more than K - 4 inputs from within the cell (K is LUT size) and the number of sink LUTs of the cell does not exceed the number of source LUTs. Presented algorithms serve to answer the posed question, but, due to area-inefficiency, do not have much practical value at this point.

关键词： periodic graphs routing algorithms universality proofs fixed interconnect hard-wired fpgas

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A Flexible Toolflow for Mapping CNN Models to High Performance fpga-based Accelerators 23

A Flexible Toolflow for Mapping CNN Models to High Performan...

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Proceedings of the 2023 acm/sigda international symposium on field programmable gate arrays

作者： Yongzheng Chen Gang Wu Northeastern University Shenyang China

ISBN: (纸本)9781450394178

There have been many studies on developing automatic tools for mapping CNN models onto fpgas. However, challenges remain in designing an easy-to-use toolflow. First, the toolflow should be able to handle models exported from various deep learning frameworks and models with different topologies. Second, the hardware architecture should make better use of on-chip resources to achieve high performance. In this work, we build a toolflow upon Open Neural Network Exchange (ONNX) IR to support different DL frameworks. We also try to maximize the overall throughput via multiple hardware-level efforts. We propose to accelerate the convolution operation by applying parallelism not only at the input and output channel level, but also at the output feature map level. Several on-chip buffers and corresponding management algorithms are also designed to leverage abundant memory resources. Moreover, we employ a fully pipelined systolic array running at 400 MHz as the convolution engine, and develop a dedicated bus to implement the im2col algorithm and provide feature inputs to the systolic array. We generated 4 accelerators with different systolic array shapes and compiled 12 CNN models for each accelerator. Deployed on a Xilinx VCU118 evaluation board, the performance of convolutional layers can reach 3267.61 GOPS, which is 99.72% of the ideal throughput (3276.8 GOPS). We also achieve an overall throughput of up to 2424.73 GOPS. Compared with previous studies, our toolflow is more user-friendly. The end-to-end performance of the generated accelerators is also better than that of related work at the same DSP utilization.

关键词： field-programmable gate array (fpga) toolflow convolutional neural network (CNN) systolic array memory management

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fpga Acceleration of the Horn and Schunck Hierarchical Algorithm

FPGA Acceleration of the Horn and Schunck Hierarchical Algor...

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IEEE international symposium on Circuits and Systems

作者： Ilias Bournias Roselyne Chotin Lionel Lacassagne CNRS LIP6 Sorbonne Université Paris France

This work proposes a highly tunable motion estimation architecture. We implement the Horn and Schunck algorithm with the hierarchical extension for larger motion estimations in fpgas. Different architectures are explored dealing with interpolation, pipeline, parallelism and arithmetic format, in order to fit performance. We show in our exploration, how the different cores of our system should be used to increase the throughput. Our smallest design achieves a 30.8 Mpixel/s in a 1024×1024 resolution and the fastest 507 Mpixel/s which is one of the fastest ever achieved, as far as we know, for fpgas.

关键词： Motion estimation Pipelines Parallel processing Throughput System-on-chip Space exploration field programmable gate arrays

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Efficient fpga Implementation of Conjugate Gradient Methods for Laplacian System using HLS 19

Efficient FPGA Implementation of Conjugate Gradient Methods ...

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Proceedings of the 2019 acm/sigda international symposium on field-programmable gate arrays

作者： Sahithi Rampalli Natasha Sehgal Ishita Bindlish Tanya Tyagi Pawan Kumar International Institute of Information Technology Hyderabad India

ISBN: (纸本)9781450361378

In conjugate gradient method to solve partial differential equations, matrix vector operations are required in each iteration; these matrix vector operations can be implemented as 5 point finite difference stencil operations on the grid without explicitely constructing the matrix. We show that a pipelined and superscalar design using high level synthesis (HLS) leads to a significant reduction in latencies for two variants of conjugate gradient methods considered. When comparing these two, we show that the second method has roughly two times lower latency than the former given the same degree of superscalarity. These reductions in latencies for the newer variant of CG is due to parallel implementations of stencil operation on subdomains of the grid, and due to overlap of these stencil operations with dot product operations. In a superscalar design for the stencil operation, the computational domain needs to be partitioned, and boundary data needs to be copied, which requires padding. We propose a novel traversal of the grid for 2D domain decomposition that leads to reduction in latency cost involved with padding. The fpga implementation of CG is roughly 7 times faster than state-of- the-art sequential implementation, and roughly 4 times faster than state-of-the-art CUDA library parallel implementation for the linear system of dimension 10000 x 10000.

关键词： fpga high level synthesis laplace system pipelining superscalarity conjugate gradient

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Lightweight and Configurable Synchronizer and Demodulator Design for PDSCH on fpga

Lightweight and Configurable Synchronizer and Demodulator De...

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IEEE international symposium on Circuits and Systems

作者： Chongguang Yao Qiang Liu Linan Wang Qingye Zhang Honghui Tang Maoshen Zhang Tianjin Key Laboratory of Imaging and Sensing Microelectronics Technology School of Microelectronics Tianjin University China The 54th Research Institute of China Electronics Technology Group Corporation Shijiazhuang China

Targeting at small satellite applications, we propose a lightweight and configurable circuit design for synchronization and demodulation, which are the key processing steps of PDSCH receiver, on fpga. We design an elaborately pipelined circuit with balanced speed and area, by analysing the operation complexity and sharing resources among the operations. The circuit design is configurable such that the circuit can switch state at run-time to support multiple data rates and modulation schemes. Also, a parametric truncation module is realized to implement the circuit with fixed-point numbers. Experiments prove that the lightweight circuit can perform real-time processing of received data with good demodulation performance.

关键词： Small satellites Receivers Circuit synthesis Synchronization field programmable gate arrays Demodulation Switching circuits

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Constrained clock shifting for field programmable gate arrays 02

Constrained clock shifting for field programmable gate array...

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Proceedings of the 2002 acm/sigda tenth international symposium on field-programmable gate arrays

作者： Deshanand P. Singh Stephen D. Brown University of Toronto Toronto Canada

ISBN: (纸本)9781581134520

Circuits implemented in fpgas have delays that are dominated by its programmable interconnect. This interconnect provides the ability to implement arbitrary connections. However, it contains both highly capacitive and resistive elements. The delay encountered by any connection depends strongly on the number of interconnect elements used to route the connection. These delays are only completely known after the place and route phase of the CAD flow. We propose the use of Clock Shifting optimization techniques to improve the clock frequency as a post place and route *** Shifting Optimization is a technique first formalized in [4]. It is a cycle-stealing algorithm that allows one to reduce the critical path delay of a synchronous circuit by shifting the clock signals at each register. This technique allows late arriving signals to be sampled at a later point in time by intentionally introducing a skew on the clock input of the sampling register. Typical fpgas contain a number of special purpose global clock networks that distribute clock signals to every register in the chip. Unused global clock lines in fpgas can be used to distribute a finite set of clock skews to the entire circuit. We propose an efficient integer programming method to find the optimal circuit improvement for a finite set of clock skews. This technique is modified to consider inherent uncertainties present in the timing models. The uncertainty controls the aggressiveness of the optimizations as we must take great care in ensuring functionality for any range of possible timing *** results confirm intuition that more aggressive speed optimizations can be performed as timing models become more accurate. We also show that providing 4 skewed versions of the nominal clock signal results in the best delay--area tradeoff. This result is evocative as it may suggest future fpga architectures that contain greater numbers of global clock lines, as we tradeoff gains in speed for greater pow

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Performance Evaluation of Unrolled Cipher based Glitch PUF Implemented on Virtex-7

Performance Evaluation of Unrolled Cipher based Glitch PUF I...

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international symposium on Devices, Circuits and Systems (ISDCS)

作者： Yusuke Nozaki Shu Takemoto Yoshiya Ikezaki Masaya Yoshikawa Meijo Univeritsy Nagoya Japan

ISBN: (数字)9781665414784

ISBN: (纸本)9781665447508

As security technology for the IoT, the physically unclonable functions (PUFs) have attracted attention. The unrolled cipher PRINCE based glitch PUF (PG PUF) has been proposed for a lightweight application. The PUF is affected by the process rule because PUF utilizes small manufacturing variation; therefore, the evaluation with the different process rules is very important. This study evaluates PUF performance of PG PUF implemented on 28nm process fpga Virtex-7. Experimental results showed that the results of 28nm process fpga became worse compared with that of 65nm process. This study also showed the range setting of glitch generator according to the different process rules was important.

关键词： Performance evaluation Ciphers Physical unclonable function Generators Manufacturing Security field programmable gate arrays

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SHEPWM Class-D Amplifier with a Reconfigurable gate Driver Integrated Circuit

SHEPWM Class-D Amplifier with a Reconfigurable Gate Driver I...

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IEEE international symposium on Circuits and Systems (ISCAS)

作者： Nueraimaiti Aimaier Nam Ly Gabriel Nobert Yves Blaquière Nicolas Constantin Glenn Cowan Department of Electrical and Computer Engineering Concordia University Montréal Canada Department of Electrical Engineering #x00C9 cole de Technologie Supérieure Montréal Canada École de Technologie Supérieure Montréal QC Canada

A selective harmonic elimination pulse width modulation (SHEPWM) class-D amplifier (CDA) with a reconfigurable gate driver integrated circuit (IC) is proposed. The H-bridge CDA generates a three-level SHEPWM signal and cancels lower order harmonics of the switching voltage. To generate accurate pulses at the right switching angles, GaN devices are used and a reconfigurable gate driver IC is used to control the driving strength of the gate driver. The SHEPWM algorithm is implemented in an fpga and can configure the output on-the-fly. The simulation results show that the SHEPWM CDA has a 0.48 % total harmonic distortion (THD) for a 10 kHz output with an estimated switching loss of 38 mW for a GaN power transistor. It also shows that the driving strength of the gate driver has very little effect on THD, therefore the driving strength can be optimized between overshoot voltage and switching loss without concern for THD.

关键词： Simulation Switching loss Switches gate drivers Harmonic analysis Gallium nitride field programmable gate arrays

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