The ever increasing complexity of the applications result in the development of power hungry processors. There is a scarcity of standalone tools that have a good trade off between estimation speed and accuracy to esti...
详细信息
ISBN:
(纸本)9781450326711
The ever increasing complexity of the applications result in the development of power hungry processors. There is a scarcity of standalone tools that have a good trade off between estimation speed and accuracy to estimate power/energy at an earlier phase of design flow. There are very few tools that addresses the design space exploration issue based on power and energy. In this paper, we propose a virtual platform based standalone power and energy estimation tool for System-on-programmable Chip (SoPC) embedded platforms, which is independent of in-house tools. There are two steps involved in this tool development. The first step is power model generation. For the power model development, we used functional parameters to set up generic power models for the different parts of the system. This is a onetime activity. In the second step, a simulation based virtual platform framework is developed to evaluate accurately the activities used in the related power models developed in the first step. The combination of the two steps lead to a hybrid power estimation, which gives a better trade-off between accuracy and speed. The proposed tool has several benefits: it considers the power consumption of the embedded system in its entirety and leads to accurate estimates without a costly and complex material. The proposed tool is also scalable for exploring complex embedded multi-core *** effectiveness of our proposed tool is validated through dualcore RISC processor designed around the fpga board and extended to accommodate futuristic multi-core processors for a reliable energy based design space exploration. The accuracy of our proposed tool is evaluated by using a variety of industrial benchmarks such as Multimedia, EEMBC and SPEC2006. Estimated power values are compared to real board measurements and also to McPAT. Our obtained power/energy estimation results provide less than 9% of error for heterogeneous MPSoC based system and are 200% faster compared to other
Zero-phase component analysis (ZCA) is a promising de-correlation technique in data pre-processing. It avoids stochastic axis swapping issues that prevailed in other preprocessing methods. ZCA evaluation of a signal h...
详细信息
ISBN:
(纸本)9798350399233
Zero-phase component analysis (ZCA) is a promising de-correlation technique in data pre-processing. It avoids stochastic axis swapping issues that prevailed in other preprocessing methods. ZCA evaluation of a signal has three major computational units such as (i) covariance matrix, (ii) eigenvalue decomposition and (iii) whitened matrix. Eigenvalue decomposition is an intensive computational unit in ZCA. In this paper, we implemented the ZCA algorithm on a PYNQ fpga platform using HW-SW co-design framework to achieve hardware acceleration. Firstly, we implemented eigenvalue decomposition using Lanczos and implicit TriQR algorithm as a hardware IP and computed its hardware acceleration on PYNQ-Z1 fpga. Secondly, we partitioned the ZCA algorithm as (i) covariance matrix and whitened matrix evaluation on processing unit and eigen decomposition unit on hardware IP, (ii) covariance matrix evaluation on processing unit and eigen decomposition unit along with the whitened matrix evaluation on hardware IP. The complete ZCA whitening system was designed using the AXI-Lite interface between the processor and hardware IP logic unit. The hardware acceleration factor and the resource utilization for ZCA whitening are reported for different input dimensions. The implementation results demonstrate that the HW-SW co-design attained hardware acceleration of 8x to 18x for varied input data feature dimensions between $1000\times 10$ and $1000\times 20$ .
IoT devices are being used in different environments recently. They are mostly resource-constrained, and therefore, their data security is crucial. Several lightweight cryptographic primitives were proposed to overcom...
详细信息
ISBN:
(纸本)9781665465007
IoT devices are being used in different environments recently. They are mostly resource-constrained, and therefore, their data security is crucial. Several lightweight cryptographic primitives were proposed to overcome the limitations of the devices while maintaining moderate security levels. Such primitives provide either encryption or authentication. The encryption must be authenticated by a Message Authentication Code (MA C) or hash function for better overall security. Therefore, an architecture of integrated lightweight authenticated encryption (AE) based on LED block cipher and PHOTON hash function is presented. LED and PHOTON architectures were combined while exploiting area-performance trade-offs and utilizing the shared internal functions. The architecture is designed in Verilog HDL, synthesized in Altera Quartus II and simulated on fieldprogrammablegate Array (fpga) devices. The individual design of LED utilizes 357 logic elements (LE) and PHOTON utilizes 852 LE resulting in a total of 1209 LE. The logic utilization of the proposed shared architecture is 1046 LE. The results reveal that 13.5 % reduction in logic area is achieved compared to the independent implementations of LED and PHOTON.
暂无评论