The proceedings contain 211 papers. The topics discussed include: a reference-free phase noise measurement circuit achieving 24.2 fs periodic jitter sensitivity and 275 fsrms resolution with background self-calibratio...
ISBN:
(纸本)9781665497725
The proceedings contain 211 papers. The topics discussed include: a reference-free phase noise measurement circuit achieving 24.2 fs periodic jitter sensitivity and 275 fsrms resolution with background self-calibration;a 17–95.6 TOPS/W deep learning inference accelerator with per-vector scaled 4-bit quantization for transformers in 5nm;2.4GHz, double-buffered, 4kb standard-cell-based register file with low-power mixed-frequency clocking for machine learning accelerators;neuro-CIM: a 310.4 TOPS/W neuromorphic computing-in-memory processor with low WL/BL activity and digital-analog mixed-mode neuron firing;a 640×480 indirect time-of-flight image sensor with tetra pixel architecture for tap mismatch calibration and motion artifact suppression;a 4-tap CMOS time-of-flight image sensor with in-pixel analog memory array achieving 10kfps high-speed range imaging and depth precision enhancement;a first-order continuous-time noise-shaping SAR ADC with duty-cycled integrator;helix: an electrochemical CMOS DNA synthesizer;Amber: a 367 GOPS, 538 GOPS/W 16nm SOC with a coarse-grained reconfigurable array for flexible acceleration of dense linear algebra;MAQO: a scalable many-core annealer for quadratic optimization;and a 39,000 subexposures/s CMOS image sensor with dual-tap coded-exposure data-memory pixel for adaptive single-shot computational imaging.
The proceedings contain 249 papers. The topics discussed include: on the reliability of high-performance dual gate (DG) W-doped In2O3 FET;a 12-bit 10GS/s time-interleaved SAR ADC with even/odd channel-correlated absol...
ISBN:
(纸本)9798350361469
The proceedings contain 249 papers. The topics discussed include: on the reliability of high-performance dual gate (DG) W-doped In2O3 FET;a 12-bit 10GS/s time-interleaved SAR ADC with even/odd channel-correlated absolute error-based over-Nyquist timing-skew calibration in 5nm FinFET;14nm FinFET node embedded MRAM technology for automotive non-volatile RAM applications with endurance over 1E12-cycles;an intra-body-power-transfer system energized by an electromagnetic energy harvester for powering wearable sensor nodes;first demonstration of high retention energy barriers and 2 ns switching, using magnetic ordered-alloy-based STT MRAM devices;cell to core-periphery overlap (C2O) based on BCAT for next generation DRAM;and a 25.4–27.5GHz ping-pong charge-sharing locking PLL achieving 42fs jitter with implicit reference frequency doubling.
The proceedings contain 229 papers. The topics discussed include: a wireless sensor-brain interface system for tracking and guiding animal behaviors through goal-directed closed-loop neuromodulation;a wireless neural ...
ISBN:
(纸本)9784863488069
The proceedings contain 229 papers. The topics discussed include: a wireless sensor-brain interface system for tracking and guiding animal behaviors through goal-directed closed-loop neuromodulation;a wireless neural stimulator IC for cortical visual prosthesis;a 1,024-channel, 64-interconnect, capacitive neural interface using a cross-coupled microelectrode array and 2-dimensional code-division multiplexing;a wireless, mechanically flexible, 25μm-thick, 65,536-channel subdural surface recording and stimulating microelectrode array with integrated antennas;a fully synthesizable 100Mbps edge-chasing true random number generator;ECC-less multi-level SRAM physically unclonable function and 127% PUF-to-memory capacity ratio with no bitcell modification in 28nm;a static contention-free dual-edge-triggered flip-flop with redundant internal node transition elimination for ultra-low-power applications;a sub-THz full-duplex phased-array transceiver with self-interference cancellation and lo feedthrough suppression;an indirect time-of-flight CMOS image sensor achieving sub-ms motion lagging and 60fps depth image from on-chip ISP;and a monolithic amorphous-selenium/CMOS small-pixel-effect-enhanced X-ray-energy-discriminating quantum-counting pixel for biomedical imaging.
Nanosheet FETs (NSFETs) are considered promising candidates to replace FinFETs as the dominant devices in sub-5-nm processes. To encourage further research into NSFET-based integrated circuits, we present Virtual_N2_P...
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Nanosheet FETs (NSFETs) are considered promising candidates to replace FinFETs as the dominant devices in sub-5-nm processes. To encourage further research into NSFET-based integrated circuits, we present Virtual_N2_PDK, a predictive process design kit (PDK) for 2-nm NSFET technology. All assumptions are based on publicly available sources. Ruthenium (Ru) interconnects are employed for the buried power rail (BPR) and tight-pitch layers. Wrap-around contact (WAC) is also integrated into Virtual_N2_PDK to investigate its impact on circuit performance. By calibrating the BSIM-CMG model with 3-D technology computer-aided design (TCAD) electrothermal simulation results, SPICE models that account for self-heating effects (SHEs) are generated for devices with and without WAC. The simulation results show that with the WAC structure, the energy-delay product (EDP) of standard cells is reduced by an average of 25.18%, while the frequency of a 15-stage ring oscillator circuit increases by 26.05%.
A compact half-mode substrate-integrated waveguide (HMSIW) dual-band bandpass filter (BPF) is proposed based on the through silicon vias (TSVs) technology in this brief. The two pass bands of the filter operating at 1...
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A compact half-mode substrate-integrated waveguide (HMSIW) dual-band bandpass filter (BPF) is proposed based on the through silicon vias (TSVs) technology in this brief. The two pass bands of the filter operating at 14.02 and 21.46 GHz with the 3-dB fractional bandwidth (FBW) of 32.2% and 27.5% are constructed by the quasi-TEM and TE102 modes, respectively. 3-D-stacked inductors utilizing TSVs and redistribution layers (RDLs) are employed to induce mixed couplings, thereby generating a transmission zero (TZ) above the passband, which are analyzed by the equivalent circuit of the filter. The circuit size of the fabricated prototype of the dual-band HMSIW BPF is 0.18 lambda(2)(g) . The in-band insertion losses (ILs) are 1.37 and 1.33 dB, severally. Measurement results agree well with the electromagnetic (EM) simulation results.
作者：
Wang, YaotingWu, YongyuGao, DaweiXu, KaiZhejiang Univ
Coll Integrated Circuits Hangzhou Zhejiang Peoples R China Zhejiang Univ
Coll Integrated Circuits ZJU Hangzhou Global Sci & Technol Innovat Ctr Hangzhou 311200 Zhejiang Peoples R China Zhejiang Univ
Zhejiang Technol Innovat Ctr CMOS IC Mfg Proc & De Hangzhou 311200 Zhejiang Peoples R China
Line Width Roughness (LWR) has emerged as a pivotal challenge that the semiconductor manufacturing industry must confront. This study provides experimental data to elucidate the mechanism by which LWR affects device p...
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Line Width Roughness (LWR) has emerged as a pivotal challenge that the semiconductor manufacturing industry must confront. This study provides experimental data to elucidate the mechanism by which LWR affects device performance in different processing layers. First, Hard Mask (HM) technology was used to reduce LWR of Active Area (AA) and polysilicon gate by 0.97 nm and 0.62 nm, respectively, resulting in a 21.79% and 55.82% decrease in threshold voltage variability. With the application of HM technology in AA layer processing, the device performance of NMOS and PMOS was also improved by 19.58% and 12.54%, respectively. This improvement can be attributed to the mitigation of carrier scattering induced by LWR. Moreover, HM technology was also conducted in polysilicon gate process which can reduce LWR effectively, thereby enhancing device stability, decreasing the drain-induced barrier lowering factor by approximately 10%, and suppressing gate-induced drain leakage current and overlap capacitance. Consequently, this process contributes to the alleviation of short channel effects. Our research provides experimental groundwork for diminishing LWR, supplies guidelines for understanding the distinct mechanisms of LWR, and offers effective route toward enhancing device performance, and controlling fluctuations.
Considered a next-generation error-correction solution, non-binary low-density parity-check (NB-LDPC) codes exhibit remarkable correcting capabilities, outperforming binary counterparts for severe channel conditions. ...
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Considered a next-generation error-correction solution, non-binary low-density parity-check (NB-LDPC) codes exhibit remarkable correcting capabilities, outperforming binary counterparts for severe channel conditions. However, contemporary decoder designs encounter challenges due to the demanding hardware resources required by their high processing complexity. In this work, we propose a novel column-wise trellis min-max (CW-TMM) algorithm, which significantly reduces the sorter overheads in the existing TMM method without degrading the error-correcting power. We also deploy the message compression to the trellis-based algorithm for effectively reducing hardware costs, even allowing the storage-aware long codes by accommodating large-sized on-chip memories. Through the integration of advanced low-cost optimization schemes together, the prototype CW-TMM decoder in a 28-nm CMOS technology for 4-kB 0.9-rate NB-LDPC codes demonstrates a 54% reduction in on-chip memory size and a 63% decrease in decoding complexity, enhancing the area efficiency by more than 2.4 times than the state-of-the-art approaches.
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