The proceedings contain 324 papers. The topics discussed include: scalable spintronics-based Bayesian neural network for uncertainty estimation;countering uncertainties in in-memory-computing platforms with statistica...
ISBN:
(纸本)9783981926378
The proceedings contain 324 papers. The topics discussed include: scalable spintronics-based Bayesian neural network for uncertainty estimation;countering uncertainties in in-memory-computing platforms with statistical training, accuracy compensation and recursive test;MAVFI: an end-to-end fault analysis framework with anomaly detection and recovery for micro aerial vehicles;formal analysis of timing diversity for autonomous systems;design enablement flow for circuits with inherent obfuscation based on reconfigurable transistors;the fora european training network on fog computing for robotics and industrial automation;VE-FIDES: designing trustworthy supply chains using innovative fingerprinting implementations;digital emulation of oscillator Ising machines;energy-efficient Bayesian inference using near-memory computation with memristors;towards a robust multiply-accumulate cell in photonics using phase-change materials;and real-time fully unsupervised domain adaptation for lane detection in autonomous driving.
The proceedings contains 142 papers from the design, automation and test in europe conference and exhibition. Topics discussed include: hybrid architectural dynamic thermal management, value-conscious cache;arithmetic...
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ISBN:
(纸本)0769520855
The proceedings contains 142 papers from the design, automation and test in europe conference and exhibition. Topics discussed include: hybrid architectural dynamic thermal management, value-conscious cache;arithmetic reasoning in DPLL-based SAT solving;enhanced diameter bounding via structural transformation;design of routing-constrained low power scan chains;digital background gain error correction in pipeline ADCs and a crosstalk aware interconnect with variable cycle transmission.
The proceedings contains 59 papers from the conference on designers' Forum - design, automation and test in europe conference and exhibition, date 04. The topics discussed include: highly digital, low-cost design ...
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ISBN:
(纸本)0769520855
The proceedings contains 59 papers from the conference on designers' Forum - design, automation and test in europe conference and exhibition, date 04. The topics discussed include: highly digital, low-cost design of statistic signal acquisition in SoCs;low power analyogue 90 degree phase shifter;an inductance modeling flow seamlessly integrated in the RF IC design chain;design of very deep pipelined multipliers for FPGAs;channel decoder architecture for 3G mobile wireless terminals;a scalable implementation of a reconfigurable WCDMA rake reciever and modeling and analysis of heterogenous industrial networks architectures.
The proceedings contains 123 papers from the design, automation and test in europe conference and exhibition: Volume II. Topics discussed include: a mapping strategy for resource-efficient network processing on multip...
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ISBN:
(纸本)0769520855
The proceedings contains 123 papers from the design, automation and test in europe conference and exhibition: Volume II. Topics discussed include: a mapping strategy for resource-efficient network processing on multiprocessor SoCs;exploiting crosstalk to speed up on-chip buses;impact of test point insertion on silicon area and timing during layout;tuning-in-sensor data filtering to reduce energy consumption in wireless sensor networks;bandwidth-constrained mapping of cores onto NoC architectures;synthesis and optimizations of threshold logic networks with application to nanotechnologies;a framework for battery-aware sensor management;and design optimization of multi-cluster embedded systems for real-time applications.
The proceedings contain 282 papers. The topics discussed include: full-stack quantum computing systems in the NISQ era: algorithm-driven and hardware-aware compilation techniques;tweedledum: a compiler companion for q...
ISBN:
(纸本)9783981926361
The proceedings contain 282 papers. The topics discussed include: full-stack quantum computing systems in the NISQ era: algorithm-driven and hardware-aware compilation techniques;tweedledum: a compiler companion for quantum computing;exploring standard-cell designs for reconfigurable nanotechnologies: a formal approach;majority-based design flow for AQFP superconducting family;a software architecture to control service-oriented manufacturing systems;comprehensive and accessible channel routing for microfluidic devices;energy-efficient brain-inspired hyperdimensional computing using voltage scaling;estimating vulnerability of all model parameters in DNN with a small number of fault injections;exploiting arbitrary paths for the simulation of quantum circuits with decision diagrams;and a novel neuromorphic processors realization of spiking deep reinforcement learning for portfolio management.
The proceedings contain 329 papers. The topics discussed include: vehicle sequence reordering with cooperative adaptive cruise control;lightweight hardware support for selective coherence in heterogeneous manycore acc...
ISBN:
(纸本)9783981926323
The proceedings contain 329 papers. The topics discussed include: vehicle sequence reordering with cooperative adaptive cruise control;lightweight hardware support for selective coherence in heterogeneous manycore accelerators;machine learning based routing congestion prediction in FPGA high-level synthesis;learning to skip ineffectual recurrent computations in LSTMs;planning with real-time collision avoidance for cooperating agents under rigid body constraints;power and performance optimal NoC design for CPU-GPU architecture using formal models;increasing accuracy of timing models: from CPA to CPA+;hard real-time scheduling of streaming applications modeled as cyclic CSDF graphs;scaling up network centrality computations;SACHa: self-attestation of configurable hardware;scalable Boolean methods in a modern synthesis flow;and non-intrusive self-test library for automotive critical applications: constraints and solutions.
The proceedings contain 307 papers. The topics discussed include: a method for power abstraction and simulation of hardware components at system level;auto-tuning techniques for compiler optimization;system-level desi...
ISBN:
(纸本)9783981537062
The proceedings contain 307 papers. The topics discussed include: a method for power abstraction and simulation of hardware components at system level;auto-tuning techniques for compiler optimization;system-level design of embedded systems for reliability;analyzing systems for correct implementation of robustness;proactive power and thermal aware optimizations for energy-efficient cloud computing;enabling caches in probabilistic timing analysis;resilient design for three-dimensional integrated circuits;low-power high-performance high-reliable spintronic design;automatic reconfigurable platforms design;robust image processing hardware acceleration on reconfigurable devices for critical applications;novel reliability estimation techniques for nano-scale circuits affected by noise, process variations and aging;analysis, design, and optimization of embedded control systems;and design and formal analysis of run-DMC, a dynamically-scheduled real-time memory controller.
The proceedings contain 301 papers. The topics discussed include: trade offs in the design of a router with both guaranteed and best-effort services for networks on chip;communication centric architectures for turbo-d...
The proceedings contain 301 papers. The topics discussed include: trade offs in the design of a router with both guaranteed and best-effort services for networks on chip;communication centric architectures for turbo-decoding on embedded multiprocessors;packetized on-chip interconnect communication analysis for MPSoC;system level specification in lava;formal semantics of synchronous systemC;systemC-AMS requirements, design objectives and rationale;parallel processing architectures for reconfigurable systems;different approaches to add reconfigurability in a SoC architecture;creating value through test;data space oriented scheduling in embedded systems;an efficient hash table based approach to avoid state space explosion in history driven quasi-static scheduling;and a novel metric for interconnect architecture performance.
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