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检索条件"任意字段=2023 European Data Handling and Data Processing Conference for Space, EDHPC 2023"

共 417 条记录，以下是91-100 订阅

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Insight4EO Architecture to Support Onboard AI Multiapplications from the End-User

Insight4EO Architecture to Support Onboard AI Multiapplicati...

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2023 european data handling and data processing conference for space, edhpc 2023

作者： Perez-Villar, Juan Ignacio Bravo Elorza, Alvaro Moron Jorcano, Enrique Sepulveda Hinz, Robert De Oliveira, Andre Batista Pavon, Jose Antonio Pulido Kerr, Murray Flight Segment Deimos Space Madrid Spain Flight Segment Deimos Engenharia Lisboa Portugal

ISBN: (纸本)9789090379241

Moving EO products onboard the spacecraft enables new scenarios of application. data prioritization techniques can be applied to discard data without meaningful content to save bandwidth and power, or emergency management solutions can be employed to obtain timely alerts on ground even before the bulk data is available. However, the deployment of such solutions onboard the spacecraft presents two main challenges. First, EO products often require L1/L2 data that is not natively available onboard the spacecraft. Second, a suitable, easy to use, execution environment is needed to obtain the EO product with low latency. The Insight4EO solution presented here solves these two main problems by providing a L1/L2 product optimised to be run onboard the spacecraft for both SAR and optical payloads and a multiapplication processing enviroment based on Multi-Processor and FPGA. © 2023 ESA.

关键词： spacecraft

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Error Rate Estimation of DDR4-SDRAM Buffers in space Mass Memories

Error Rate Estimation of DDR4-SDRAM Buffers in Space Mass Me...

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2023 european data handling and data processing conference for space, edhpc 2023

作者： Dirkes, Timo Spindeldreier, Christian Grurmann, Kai Rust, Jochen Wyrwoll, Vanessa Poppe, Bjorn DSI Aerospace GmbH Bremen Germany Hamburg University of Applied Sciences Hamburg Germany Carl von Ossietzky Universität Oldenburg Oldenburg Germany

ISBN: (纸本)9789090379241

DDR4-SDRAMs are key components widely used in modern computing systems on ground and in future space applications, where the sensitivity to ionizing radiation effects and the corresponding data integrity performance is of special interest. In this paper, an example DDR4-SDRAM buffer memory partition inside a high-performance mass memory system is described. For this buffer, two different EDAC implementations, which are Reed-Solomon single-symbol-error-correction and Reed-Solomon double-symbol-error-correction are compared in terms of data integrity performance. This comparison is based on the word error probabilities taking into account DDR4-SDRAM component specific single event effects and possible mitigation such as scrubbing and power cycling. The approach described in this work quantifies the design decision for a certain EDAC architecture as well as highlighting the impact of design parameters such as scrubbing and power cycling periods. © 2023 ESA.

关键词： space applications

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Towards a Parallel Benchmark for space Applications: Distributing OBPMark's Image processing

Towards a Parallel Benchmark for Space Applications: Distrib...

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2023 european data handling and data processing conference for space, edhpc 2023

作者： Elbarrawy, Mahmoud M. Cortes, Carlos Gonzalez Lund, Andreas Ludtke, Daniel Institute for Software Technology Braunschweig Germany Institute for Software Technology Weßling Germany

ISBN: (纸本)9789090379241

Modern space applications require high computing power and high reliability from on-board processors. To meet these requirements, the German Aerospace Center (DLR) is developing a Scalable On-board Computer for space Avionics (ScOSA) system with a distributed non-shard memory architecture. As performance is an important criterion in the selection of hardware for space missions, the european space Agency has published an open source benchmark suite called OBPMark. It is a set of benchmarks based on typical space applications and designed to measure system-level performance. However, there is currently no standard tool for evaluating the performance of distributed on-board computers. In this paper, we propose a parallelization strategy for running the OBPMark image processing benchmark on a distributed on-board computer. We used a split-map-reduce model to integrate the #1.1 image calibration and correction benchmark of OBPMark into the ScOSA system. We evaluated the developed distributed benchmark on the existing ScOSA High Performance Nodes (HPNs) consisting of 5 Xilinx Zynq 7020 SoCs. The results show a significant reduction of the benchmark execution time from 9.0 to 2.8 seconds using 5 nodes. In the case of dual-core with 4 nodes, the execution time was reduced to 2.5 seconds. We conclude that OBPMark is a valuable tool for evaluating the performance of distributed on-board computers with non-shared memory architectures and contributes to the standardisation of performance evaluation in the space domain. © 2023 ESA.

关键词： space applications

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Solar Orbiter: data handling Lessons Learned

Solar Orbiter: Data Handling Lessons Learned

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2023 european data handling and data processing conference for space, edhpc 2023

作者： Lakey, Daniel Siegle, Felix CGI Germany OPS-OPS European Space Agency / ESOC Darmstadt Germany European Space Agency / ESTEC TEC-EDD Noordwijk Netherlands

ISBN: (纸本)9789090379241

The ESA/NASA Solar Orbiter launched on 10th February 2020, to start its mission to obtain detailed measurements of the inner heliosphere and the nascent solar wind, will also perform close observations of the polar regions of the Sun. It is equipped with a suite of ten payload instruments comprising both remote sensing and in-situ sensors. The instruments communicate to the onboard mass memory over a spaceWire 'network' comprising several interconnected routers which are part of the mass memory unit. Communications between instruments and the on-board computer are also through this network, with all traffic passing through the mass memory unit. This network topology has resulted in multiple problems in-flight which we consider to be architectural problems with the everything-through-the-mass- memory approach. Problems have occurred with individual instruments, with the mass memory unit and with the mass memory / on-board computer link;the architecture of the spaceWire network has meant that in most cases the failures rapidly affect all of the connected units, either by dropping packets or link disconnection events. That is, if someone has a problem, everyone has a problem. This paper will look in detail at each of the failure cases and establish how the network architecture was a contributing factor. In contrast, the platform units are all connected on a classic MIL-STD-1553b bus with fixed data frames, which has been extremely robust despite occasional unit-level communications error. We compare and contrast the two approaches and extrapolate lessons which can be learned for future complex deep-space missions. © 2023 ESA.

关键词： data handling

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GR740 Payload Controller Module-ADHA Compliant Next Generation processing Module

GR740 Payload Controller Module-ADHA Compliant Next Generati...

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2023 european data handling and data processing conference for space, edhpc 2023

作者： Palomo, Alfonso Gonzalo Garcia Nunez, Enrique Airbus Crisa Engineering / Product Policy Spain Airbus Crisa Engineering / Digital Design Spain

ISBN: (纸本)9789090379241

The GR740 Payload Controller Module (GR740 PCM) currently in development at Airbus Crisa is based on the high-performance multi-core GR740 System-On-Chip (SoC) and the RTG4 reprogrammable FPGA which allow to provide a flexible HW architecture. This module is compatible with an ESA's Advanced data handling Architecture (ADHA) System Slot for payload application while providing additional performances, maximizing the modularity and scalability of the product. The current development will result in an Engineering Model (EM) that will go through a complete HW characterization, including ambient thermal tests, leading to a TRL6 maturity level. © 2023 ESA.

关键词： data handling

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A Hardware/Software Design space Exploration for Efficient Video Compression on ESA missions

A Hardware/Software Design Space Exploration for Efficient V...

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2023 european data handling and data processing conference for space, edhpc 2023

作者： Machado, Felipe Barrios, Yubal Sarmiento, Roberto Sanjuan, Francisco Fiengo, Aniello University of Las Palmas de Gran Canaria Institute for Applied Microelectronics Las Palmas de Gran Canaria35017 Spain Thales Alenia Space in Spain Madrid28760 Spain European Space Agency Noordwijk2201 Netherlands

ISBN: (纸本)9789090379241

Electronics design of complex systems is not trivial when it is directly addressed at RTL. Under highly timing-constrained projects, such as space missions, it is useful to quickly develop a system model with a higher level of abstraction than RTL to identify critical processing stages that could prevent from achieving design goals in terms of performance, hardware occupancy and/or power consumption. At the same time, the development time at RTL could be reduced, since some of the main issues are already detected and solved in the high-level model. This work presents a mixed DSE strategy, combining software profiling with HLS models. While software profiling allows to quickly identify the critical stages of the system functionality from a computational point of view, the HLS design methodology permits to evaluate those critical system stages but considering their implications when the design is implemented on hardware. The use case is the development of a video compression IP core for future ESA missions, compliant with the H.264 standard, which is a highly-parameterized algorithm with several features. Therefore, at early stages it is important to restrict the options of the standard to those that will keep the project performance goals while limiting the hardware occupancy. © 2023 ESA.

关键词： High level synthesis

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OBC-Ultra, the rad-hard NG-Ultra-based on Board Computer for future applications

OBC-Ultra, the rad-hard NG-Ultra-based on Board Computer for...

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2023 european data handling and data processing conference for space, edhpc 2023

作者： Danard, Estelle Comolet-Tirman, Adrien Airbus Defence and Space France

ISBN: (纸本)9789090379241

This paper will present the OBC-Ultra, the new generation of On Board Computer developed by Airbus and based on the european rad-hard *** OBC-Ultra is the new generation of Airbus On Board Computer (OBC) targeting both Telecommunication and Earth Observation missions. It is based on the european rad-hard FPGA and SoC from NanoXplore named the *** new equipment directly benefits from the Airbus database and experience acquired through several H2020, GSTP and internal RandD projects on NG-Ultra-based applications, from generic VHDL and Low Level Software (SW) libraries to place and route automatisation and optimisation of FPGA *** presentation will describe the architecture of this new NG-Ultra-based OBC by presenting the VHDL and low level software modules and by explaining how the use of NanoXplore components allows the attainment of high data rate performances across the different boards while offering a european-based solution critical for our strategic non-dependence:•Wide range of communication protocols (SPW, CAN, 1553, RS485) on NG-Ultra-based processing board•Critical functions (Reconf, Security, ETC, ETM) on Ultra-300-based board without SW•20Mbps TM/TC distributed across 2 boards for both SW performances and HW critical functions independence•Latest space data Link Security (SDLS) Extended Procedures standard support•Mass Memory function on processing board with Flash NAND and HW autonomous modules•Advanced HW and SW Debug and Trace features•Carefully considered HW/SW architecture for complex, multicore SW and critical autonomous HW.•Boards respecting modular ADHA standardThis presentation will be an opportunity for Airbus to detail the current development status of OBC-Ultra. © 2023 ESA.

关键词： Field programmable gate arrays (FPGA)

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After six months successful operations in low earth orbit: data processing system architecture and lessons learned from the LisR mission

After six months successful operations in low earth orbit: D...

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2023 european data handling and data processing conference for space, edhpc 2023

作者： Konstantin, Schafer Andreas, Brunn Clemens, Horch Marius, Bierdel Atin, Jain Frank, Schafer Ernst-Mach-Institut EMI Fraunhofer Institute for High-Speed Dynamics Freiburg Germany Constellr GmbH Freiburg Germany

ISBN: (纸本)9789090379241

The LisR (Longwave Infrared Sensing demonstrator) mission was a successful technology demonstrator mission conducted on the Nanoracks Experimental Platform (NREP) outside the International space Station (ISS). Launched in February 2022, the mission aimed to monitor the Earth's surface temperature using a cryo-cooled thermal infrared imager. The system components were based on commercial-off-the-shelf (COTS) components, following a New space approach. To ensure the robust operation of the COTS electronics in the Low Earth Orbit (LEO) environment, various protective measures and operational precautions were implemented. During its nearly six months in orbit, with four and a half months of operation and three and a half months of active imaging, the LisR mission achieved significant success. The payload acquired over 9.3 million frames and captured approximately 500 million km2 of land surface, providing a valuable dataset for ongoing and future research. This mission also showcased Fraunhofer EMI's onboard data processing unit for small satellites which is also used in in succeeding missions. While LisR had limitations of a rapid new space mission, it also serves as a prime example of how such an approach enables missions with limited budgets and tight schedules to achieve remarkable results. © 2023 ESA.

关键词： Field programmable gate arrays (FPGA)

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Highly Parameterised CGRA Architecture for Design space Exploration of Machine Learning Applications Onboard Satellites

Highly Parameterised CGRA Architecture for Design Space Expl...

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2023 european data handling and data processing conference for space, edhpc 2023

作者： Zulberti, Luca Monopoli, Matteo Nannipieri, Pietro Fanucci, Luca Moranti, Silvia University of Pisa Department of Information Engineering Pisa Italy European Space Research and Technology Centre Noordwijk Netherlands

ISBN: (纸本)9789090379241

The adoption of Machine Learning solutions directly onboard in satellite missions is becoming more and more attractive for the space sector. Among the various kinds of hardware accelerators, ranging from highly efficient yet inflexible COTS to more versatile FPGA-based solutions, Coarse-Grained Reconfigurable Array architectures are gaining importance in the field. CGRAs find applications in various domains, including digital signal processing, image and video processing, and cryptography, thus being considered also for space-related applications. They comprise an array of processing Elements, whose complexity is between FPGA logic cells and general-purpose processors, interconnected through a Network on Chip. They excel in handling data-flow graphs and can be more efficient than FPGAs for the execution of specific tasks. Their versatility hinges on various architectural aspects of the coarse-grained array of processing Elements. Among them, the supported operations, the possible interconnections, and the pipeline stages impact the functionality, the area, the power consumption, and the maximum frequency of the accelerator. In this work, we present a highly parameterised CGRA-based accelerator that we developed for an extensive Design space Exploration on these architectures. The description starts from the CGRA building blocks, the Functional Units, and progresses towards the top level of the architecture, represented by the Node component, which is composed of an NxM matrix of processing Elements. For each level of the hierarchy, we describe the HDL design parameters affecting the run-time reconfigurability of the accelerator, delving deeper into the functionality of the architecture. In the last section, we present synthesis results on the 40nm Standard-Cell technology from TSMC, highlighting performance, power consumption and area occupation for many different combinations of design parameters. © 2023 ESA.

关键词： Field programmable gate arrays (FPGA)

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Low-Precision Floating-Point for Efficient On-Board Deep Neural Network processing

Low-Precision Floating-Point for Efficient On-Board Deep Neu...

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2023 european data handling and data processing conference for space, edhpc 2023

作者： Gernigon, Cedric Filip, Silviu-Ioan Sentieys, Olivier Coggiola, Clement Bruno, Mickael Univ. Rennes Inria CNRS IRISA RennesF-35000 France On-Board Data Handling CNES Spacecraft Techniques Toulouse France

ISBN: (纸本)9789090379241

One of the major bottlenecks in high-resolution Earth Observation (EO) space systems is the downlink between the satellite and the ground. Due to hardware limitations, on-board power limitations or ground-station operation costs, there is a strong need to reduce the amount of data transmitted. Various processing methods can be used to compress the data. One of them is the use of on-board deep learning to extract relevant information in the data. However, most ground-based deep neural network parameters and computations are performed using single-precision floating-point arithmetic, which is not adapted to the context of on-board processing. We propose to rely on quantized neural networks and study how to combine low precision (mini) floating-point arithmetic with a Quantization-Aware Training methodology. We evaluate our approach with a semantic segmentation task for ship detection using satellite images from the Airbus Ship dataset. Our results show that 6-bit floating-point quantization for both weights and activations can compete with single-precision without significant accuracy degradation. Using a Thin U-Net 32 model, only a 0.3% accuracy degradation is observed with 6-bit minifloat quantization (a 6-bit equivalent integer-based approach leads to a 0.5% degradation). An initial hardware study also confirms the potential impact of such low-precision floating-point designs, but further investigation at the scale of a full inference accelerator is needed before concluding whether they are relevant in a practical on-board scenario. © 2023 ESA.

关键词： Deep neural networks

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