The proceedings contain 12 papers. The topics discussed include: neuro-symbolic architecture meets large language models: a memory-centric perspective;work-in-progress: context and noise aware resilience for autonomou...
ISBN:
(纸本)9798350356397
The proceedings contain 12 papers. The topics discussed include: neuro-symbolic architecture meets large language models: a memory-centric perspective;work-in-progress: context and noise aware resilience for autonomous driving applications;tutorial on novel toolkits toward AI for science on resource-constrained computing systems;work-in-progress: worst-case execution-time measurement techniques for nonlinear model predictive controllers;end-to-end carbon footprint assessment and modeling of deep learning;estimation and optimization of DNNs for embedded platforms;emerging architecture design, control, and security challenges in software defined vehicles;***: principles and practices of machine learning systems engineering;AI-driven indoor navigation with mobile embedded systems;sustainable deployment of deep neural networks on non-volatile compute-in-memory accelerators;and reducing smart phone environmental footprints with in-memory processing.
The proceedings contain 61 papers from the Codes+ISSS 2005 - internationalconference on hardware/softwarecodesign and systemsynthesis. The topics discussed include: hardware and software architecture for the CELL p...
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ISBN:
(纸本)1595931619
The proceedings contain 61 papers from the Codes+ISSS 2005 - internationalconference on hardware/softwarecodesign and systemsynthesis. The topics discussed include: hardware and software architecture for the CELL processor;performance and power analysis of computer systems;the challenge of embedded system design;conflict analysis in multipurpose synthesis for optimized system integration;a cycle-accurate compilation algorithm for custom pipelines datapaths;highly flexible multi-mode systemsynthesis;implementation of dynamic streaming applications on heterogeneous multi-processor architectures;and increasing on-chip memory space utilization for embedded chip multiprocessors through data compression.
The proceedings contain 45 papers from the internationalconference on hardware/softwarecodesign and systemsynthesis, CODES+ISSS 2004. The topics discussed include: future challenges in embedded systems;dual-pipelin...
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ISBN:
(纸本)1581139373
The proceedings contain 45 papers from the internationalconference on hardware/softwarecodesign and systemsynthesis, CODES+ISSS 2004. The topics discussed include: future challenges in embedded systems;dual-pipeline heterogeneous ASIP design;hardwaresynthesis from coarse-grained dataflow specification for fast HW/SW cosynthesis;memory accesses management during high level synthesis;benchmark-based design strategies for single chip heterogeneous multiprocessors;dynamic overlay of scratchpad memory for energy minimization;power-performance trade-offs for reconfigurable computing;and facilitating reuse in hardware models with enhanced type inference.
The proceedings contains 38 papers from the First IEEE/ACM/IFIP internationalconference on hardware/softwarecodesign and systemsynthesis, CODES+ISSS 2003. The topics discussed include: RTOS scheduling in transactio...
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The proceedings contains 38 papers from the First IEEE/ACM/IFIP internationalconference on hardware/softwarecodesign and systemsynthesis, CODES+ISSS 2003. The topics discussed include: RTOS scheduling in transaction level models;hardware support for real-time operating systems;a fast parallel Reed-Solomon decoder on a reconfigurable architecture;a low power scheduler using game theory;programmers' views of SoCs;and verification of design decisions in ForSyDe.
The proceedings contain 37 papers. The topics discussed include: a practical methodology to validate the statistical behavior of bloom filters;scalable and realistic benchmark synthesis for efficient NoC performance e...
ISBN:
(纸本)9781450330503
The proceedings contain 37 papers. The topics discussed include: a practical methodology to validate the statistical behavior of bloom filters;scalable and realistic benchmark synthesis for efficient NoC performance evaluation: a complex network analysis approach;an accurate and flexible early memory system power evaluation approach using a microcomponent method;how to enable software isolation and boost system performance with sub-block erase over 3D flash memory;realizing erase-free SLC flash memory with rewritable programming design;an overview of micron's automata processor;enabling the high level synthesis of data analytics accelerators;and big data analytics on heterogeneous accelerator architectures.
The proceedings contain 37 papers. The topics discussed include: a practical methodology to validate the statistical behavior of bloom filters;scalable and realistic benchmark synthesis for efficient NoC performance e...
ISBN:
(纸本)9781450344838
The proceedings contain 37 papers. The topics discussed include: a practical methodology to validate the statistical behavior of bloom filters;scalable and realistic benchmark synthesis for efficient NoC performance evaluation: a complex network analysis approach;an accurate and flexible early memory system power evaluation approach using a microcomponent method;time and timeliness;a design to reduce write amplification in object-based NAND flash devices;enabling the high level synthesis of data analytics accelerators;and going deeper than deep learning for massive data analytics under physical constraints.
The proceedings contain 11 papers. The topics discussed include: work-in-progress: what to expect of early training statistics? an investigation on hardware-aware neural architecture search;work-in-progress: high-perf...
ISBN:
(纸本)9781665472944
The proceedings contain 11 papers. The topics discussed include: work-in-progress: what to expect of early training statistics? an investigation on hardware-aware neural architecture search;work-in-progress: high-performance systolic hardware accelerator for RBLWE-based post-quantum cryptography;work-in-progress: BloCirNN: an efficient software/hardwarecodesign approach for neural network accelerators with block-circulant matrix;work-in-progress: HeteroRW: a generalized and efficient framework for random walks in graph analysis;work-in-progress: lark: a learned secondary index toward LSM-tree for resource-constrained embedded storage systems;work-in-progress: toward energy-efficient near STT-MRAM processing architecture for neural networks;work-in-progress: utilizing latency and accuracy predictors for efficient hardware-aware NAS;industry-track: towards agile design of neural processing unit;and industry paper: surrogate models for testing analog designs under limited budget – a bandgap case study.
The proceedings contain 16 papers. The topics discussed include: meta-chain: user-aware cross-layer space allocation strategy for blockchain storage systems: work-in-progress;heatmap-aware low-cost design to resist ad...
ISBN:
(纸本)9781728191980
The proceedings contain 16 papers. The topics discussed include: meta-chain: user-aware cross-layer space allocation strategy for blockchain storage systems: work-in-progress;heatmap-aware low-cost design to resist adversarial attacks: work-in-progress;layering the monitoring action for improved flexibility and overhead control: work-in-progress;a new hardware Trojan design: distinguishing between trigger inputs and functional inputs is difficult: work-in-progress;techniques for design analysis and modification based on ASAP model : work-in-progress;widerframe: an automatic customization framework for building CNN accelerators on FPGAs: work-in-progress;and an ESL methodology for HW/SW co-design of monitorable embedded systems: the 'design for monitorability' project - work-in-progress.
The proceedings contain 24 papers. The topics discussed include: how to improve the space utilization of Dedup-based PCM storage devices?;a tiny-capacitor-backed non-volatile buffer to reduce storage writes in smartph...
ISBN:
(纸本)9781467383219
The proceedings contain 24 papers. The topics discussed include: how to improve the space utilization of Dedup-based PCM storage devices?;a tiny-capacitor-backed non-volatile buffer to reduce storage writes in smartphones;lightweight virtual memory support for many-core accelerators in heterogeneous embedded SoCs;improved hard real-time scheduling of CSDF-modeled streaming applications;hardwaresynthesis from a recursive functional language;power-awareness and smart-resource management in embedded computing systems;an online wear state monitoring methodology for off-the-shelf embedded processors;big/little deep neural network for ultra low power inference;an approximate compressor for wearable biomedical healthcare monitoring systems;and fast parallel application and multiprocessor design space exploration from sequential code.
The proceedings contain 37 papers. The topics discussed include: embedded supercomputing in FPGAs with the VectorBlox MXP matrix processor;WHISK: an uncore architecture for dynamic information flow tracking in heterog...
ISBN:
(纸本)9781479914173
The proceedings contain 37 papers. The topics discussed include: embedded supercomputing in FPGAs with the VectorBlox MXP matrix processor;WHISK: an uncore architecture for dynamic information flow tracking in heterogeneous embedded SoCs;a reconfigurable real-time SDRAM controller for mixed time-criticality systems;DHeating: dispersed heating repair for self-healing NAND flash memory;synthesis-friendly techniques for tightly-coupled integration of hardware accelerators into shared-memory multi-core clusters;reducing inter-core cache contention with an adaptive bank mapping policy in DRAM cache;pvFPGA: accessing an FPGA-based hardware accelerator in a paravirtualized environment;on the automatic generation of GPU-oriented software applications from RTL IPs;CMSM: an efficient and effective code management for software managed multicores;and learning the optimal operating point for many-core systems with extended range voltage/frequency scaling.
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