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ACM/IEEE international conference on hardware/software codesign and system synthesis (CODES+ISSS)

作者： Wang, Hongfei Li, Jianwen He, Kun Cai, Wenjie Huazhong Univ Sci & Technol Sch Comp Sci & Technol Wuhan Peoples R China

ISBN: (纸本)9781538655627

Recent years witness the rapid development in hardware/software codesign that integrates machine learning (ML) models with hardware systems [1]–[4]. Despite the booming trend in building neuromorphic computing systems [2], decision trees still attract much attention in ML communities, from both software [5], [6] and hardware [1], [7], [8] approaches. A single tree model may not be as accurate as desired. One effective way to remedy this is to apply ensemble methods [5]–[7], [9]–[11], such as the Random Forest (RF) [5]. Larger tree ensembles typically improve accuracy, but demand more computation resources, especially for hardware implementation. Many methods have been proposed to address this issue. The motivation arouses from the fact that tree models usually demands much less computation resource comparing to neural networks, making them extremely potential for wearable devices and embedded systems at the edge nodes of the IoT [7], [11], [12]. Moreover, due to their inherent structures, tree ensembles are ideal for exploiting the computational parallelism on FPGA [1], [4], [7]–[9], [11], [13].

关键词： Radio frequency Vegetation hardware Field programmable gate arrays Forestry Minimization Computational modeling

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A Low Cost Acceleration Method for hardware Trojan Detection Based on Fan-out Cone Analysis 14

A Low Cost Acceleration Method for Hardware Trojan Detection...

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international conference on hardware / software codesign and system synthesis (CODES+ISSS)

作者： Zhou, Bin Zhang, Wei Thambipillai, Srikanthan Teo, J. K. J. Nanyang Technol Univ Sch Comp Engn Singapore Singapore Hong Kong Univ Sci & Technol Dept Elect & Comp Engn Hong Kong Peoples R China Harbin Inst Technol Res Ctr Basic Space Sci Harbin Heilongjiang Peoples R China

ISBN: (纸本)9781450330510

Fabless semiconductor industry and government agencies have raised serious concerns about tampering with inserting hardware Trojans in an integrated circuit supply chain in recent years. In this paper, a low hardware overhead acceleration method of the detection of HTs based on the insertion of 2-to-1 MUXs as test points is proposed. In the proposed method, the fact that one logical gate has a significant impact on the transition probability of the logical gates in its logical fan-out cone is utilized to optimize the number of the insertion MUXs. The nets which have smaller transition probability than the threshold value set by the user and minimal logical depth from the primary inputs are selected as the candidate nets. As for each candidate net, only its input net with smallest signal probability is required to be inserted the MUXs based test points until the minimal transition probability of the entire circuit is no smaller than the threshold value. Experiment results on ISCAS'89 benchmark circuits show that our proposed method can achieve remarkable improvement of transition probability with small overhead penalty.

关键词： hardware Trojan Fan-out cone Low cost Signal probability Transition probability

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Code Generation from a Domain-specific Language for C-based HLS of hardware Accelerators 14

Code Generation from a Domain-specific Language for C-based ...

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international conference on hardware / software codesign and system synthesis (CODES+ISSS)

作者： Reiche, Oliver Schmid, Moritz Hannig, Frank Membarth, Richard Teich, Juergen Friedrich Alexander Univ Erlangen NUrnberg FAU Dept Comp Sci Erlangen Germany Saarland Univ Intel Visual Comp Inst Saarbrucken Germany

ISBN: (纸本)9781450330510

As today's computer architectures are becoming more and more heterogeneous, a plethora of options including CPUs, GPUs, DSPs, reconfigurable logic (FPGAs), and other application-specific processors come into consideration for close-to-sensor processing. Especially, in the domain of image processing on mobile devices, among numerous design challenges, a very stringent energy budget is of utmost importance, making embedded GPUs and FPGAs ideal targets for implementation. Recently, the HIPA(cc) framework was proposed as a means for automatic code generation of image processing algorithms for embedded GPUs, based on a Domain-Specific Language (DSL). Despite of huge advancements in High-Level synthesis (HLS) for FPGAs, designers are still required to have detailed knowledge about coding techniques and the targeted architecture to achieve efficient solutions. As a remedy, in this work, we propose code generation techniques for C-based HLS from a common high-level DSL description targeting FPGAs. Our approach includes FPGA-specific memory architectures for handling point and local operators, numerous high-level transformations, and automatic test bench generation. We evaluate our approach by comparing the resulting hardware accelerators to existing frameworks in terms of performance and resource requirements. Moreover, we assess the achieved energy efficiency in contrast to software implementations, generated by HIPAcc from the same code base, executed on GPUs.

关键词： Code generation domain specific language image processing high-level synthesis hardware accelerator FPCA CPU

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system-level power-performance tradeoffs for reconfigurable computing

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) systemS 2006年第7期14卷 730-739页

作者： Noguera, Juanjo Badia, Rosa M. Tech Univ Catalonia Comp Architecture Dept Barcelona 08034 Spain

In this paper, we propose a configuration-aware data-partitioning approach for reconfigurable computing, We show how the reconfiguration overhead impacts the data-partitioning process. Moreover, we explore the system-level power-performance tradeoffs available when implementing streaming embedded applications on fine-grained reconfigurable architectures. For a certain group of streaming applications, we show that an efficient hardware/software partitioning algorithm is required when targeting low power. However, if the application objective is performance, then we propose the use of dynamically reconfigurable architectures. We propose a design methodology that adapts the architecture and algorithms to the application requirements. The methodology hag been proven to work on a real research platform based on Xilinx devices. Finally, we have applied our methodology, and algorithms to the case study of image sharpening, which is required nowadays in digital cameras and mobile phones.

关键词： hardware/software (HW/SW) codesign power-performance tradeoffs reconfigurable computing (RC)

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Heatmap-Aware Low-Cost Design to Resist Adversarial Attacks: Work-in-Progress

Heatmap-Aware Low-Cost Design to Resist Adversarial Attacks:...

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international conference on hardware/software codesign and system synthesis (CODES+ISSS)

作者： He, Zhiyuan Jiang, Wei Zhan, Jinyu Wang, Xupeng We, Xiangyu Univ Elect Sci & Technol China Sch Informat & Software Engn Chengdu Peoples R China

ISBN: (纸本)9781728191980

It is a challenging task to resist adversarial attacks due to the imperceptibility of adversarial examples. The passive defense method is developed based on a series of input transformations and has achieved a promising result, which however suffers from a high computation cost. In this paper, we design a new heatmap-aware method to defend adversarial attacks, leading to a significant decrease in the time cost. To he specific, we compute the classification importance from each part of the input to obtain the heatmap of the data, and the key areas of classification are extracted according to the heatmap. A series of transformations are applied to the key areas of the classification, which reduces the amount of data to be processed and thus reduces the time cost. A set of preliminary experiments are conducted to testify the effectiveness of the proposed approach.

关键词： Costs

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Fast Online synthesis of Generally Programmable Digital Microfluidic Biochips 12

Fast Online Synthesis of Generally Programmable Digital Micr...

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10th ACM international conference on hardware/software-codesign and system synthesis

作者： Grissom, Daniel Brisk, Philip Univ Calif Riverside Dept Comp Sci & Engn Riverside CA 92521 USA

ISBN: (纸本)9781450314268

We introduce an online synthesis flow for digital microfluidic biochips, which will enable real-time response to errors and control flow. The objective of this flow is to facilitate fast assay synthesis while minimally compromising the quality of results. In particular, we show that a virtual topology, which constrains the allowable locations of assay operations such as mixing, dilution, sensing, etc., in lieu of traditional placement, can significantly speed up the synthesis process without significantly lengthening assay execution time.

关键词： Microfluidics Laboratory-on-Chip (LoC) Electrowetting-on-Dielectric (EWoD) synthesis

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Proceedings of the ninth international symposium on hardware/software codesign

Proceedings of the ninth international symposium on hardware...

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9th international Symposium on hardware/software codesign

The proceedings contains 43 papers from the conference on the Proceedings of the Ninth international Symposium on hardware/software codesign. Topic discussed include: the usage of stochastic processes in embedded system specifications;modelling and evaluation of hardware/software designs;a practical toolbox for system level communication synthesis;designing domain-specific processors;a novel parallel deadlock detection algorithm and architecture;towards effective embedded processors in codesigns: customizable partitioned caches;and development cost and size estimation starting from high-level specifications.

关键词： Embedded systems

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An Energy-aware Spiking Neural Network hardware Mapping based on Particle Swarm Optimization and Genetic Algorithm

An Energy-aware Spiking Neural Network Hardware Mapping base...

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international conference on hardware/software codesign and system synthesis (CODES+ISSS)

作者： Liu, Junxiu Huang, Xingyue Jiang, Dong Luo, Yuling Guangxi Normal Univ Sch Elect Engn Guilin Peoples R China

ISBN: (纸本)9781728191980

Spiking Neuron Network (SNN) is a biological neural network model which shows great capability in the time series data processing and pattern recognition etc. according to the recent research. It has been implemented in hardware system with a good scalability, where the Networks-on-Chip (NoC) interconnection strategy is widely used for the data communications between the neurons. The mapping between a SNN and a NoC hardware system is one of the challenge for the development of the hardware SNNs. In this paper, a hybrid Particle Swarm Optimization (PSO) algorithm for hardware SNN mapping is proposed with the object of minimizing the energy consumption. Compared to the conventional PSO, it can search the mapping solutions through three directions which can speed up the finding. In the meantime, the Genetic Algorithm (GA) is combined to provide the mutation operation to avoid converging to the local optimum. A typical hardware SNN is used as the testbench and results show that an effective hardware SNN mapping is obtained with a low energy consumption, and local optimum is avoided compared to other approaches.

关键词： Spiking neural networks hardware implementation Networks-on-Chip Energy consumption

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system-on-chip validation using UML and CWL

System-on-chip validation using UML and CWL

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2nd international conference on hardware/software codesign and systems synthesis

作者： Zhu, Q Oishi, R Hasegawa, T Nakata, T Fujitsu Labs Ltd Nakahara Ku Kawasaki Kanagawa 2118588 Japan

ISBN: (纸本)1581139373

In this paper, a novel method for high-level specification and validation of SoC designs using UML is proposed. UML is introduced as a formal model of specification for SoC design. The consistency and completeness of the specification is validated based on the formal UML model. The implementation is validated by a systematic derivation of test scenarios and specification based coverage metrics from the UML model. The method has been applied to the design of a new media-processing chip for mobile devices. The application of the method shows that it is not only effective for finding logical errors in the implementation, but also eliminates errors due to inconsistency and incompleteness of the specification.

关键词： verification process UML validation and verification specification modeling

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Power-smart system-on-chip architecture for embedded cryptosystems 05

Power-smart system-on-chip architecture for embedded cryptos...

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international conference on hardware/software codesign and system synthesis

作者： Muresan, R Vahedi, H Zhanrong, Y Gregori, S Univ Guelph Sch Engn Guelph ON N1G 2W1 Canada

ISBN: (纸本)1595931619

In embedded cryptosystems, sensitive information can leak via timing, power, and electromagnetic channels. We introduce a novel power-smart system-on-chip architecture that provides support for masking these channels by controlling, in real-time, the power and the current consumption of a system to predefined programmable values. The main components of the architecture are a processor core, a current sensor module, a dynamically controlled power supply module, a clock frequency control module, and a current injection module. Real-time current measurements and power-aware voltage control are used in closed loop architecture to regulate and minimize the total power consumption of the system. Simulation results show that the current consumption of the system can be regulated to a reference level with reduced power-to-security trade off (power overhead less than 12% of the total power).

关键词： power-smart system-on-chip power analysis attack resistant architecture current flattening in hardware voltage scaling DES

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