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检索条件"任意字段=2024 International Conference on Hardware/Software Codesign and System Synthesis"
852 条 记 录,以下是101-110 订阅
排序:
Memory accesses management during high level synthesis
Memory accesses management during high level synthesis
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2nd international conference on hardware/software codesign and systems synthesis
作者: Corre, G Senn, E Bomel, P Julien, N Martin, E Univ S Brittany LESTER F-56321 Lorient France
We introduce a new approach to take into account the memory architecture and the memory mapping in behavioral synthesis. We formalize the memory mapping as a set of constraints for the synthesis, and defined a Memory ... 详细信息
来源: 评论
Cellular handset technology system requirements and integration trends
Cellular handset technology system requirements and integrat...
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2nd international conference on hardware/software codesign and systems synthesis
作者: Mattisson, S Ericsson Mobile Platforms AB Strateg Prod Management Analog Syst Design SE-22183 Lund Sweden
In ten years the cellular telephone has evolved from a tool for the professional to an indispensable consumer product with a very high market penetration. At the same time, the handset cost, weight, and standby time h... 详细信息
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Work-in-Progress: AMVP - A High Performance Virtual Platform using Parallel systemC for Multicore ARM Architectures
Work-in-Progress: AMVP - A High Performance Virtual Platform...
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ACM/IEEE international conference on hardware/software codesign and system synthesis (CODES+ISSS)
作者: Weinstock, Jan Henrik Bucs, Robert Lajos Walbroel, Florian Leupers, Rainer Ascheid, Gerd Rhein Westfal TH Aachen Aachen Germany
This paper presents AMVP - a systemC based simulator for ARM multicore platforms designed as a tool for early SW development during platform bring-up. It uses a parallel systemC simulation approach to counter the perf... 详细信息
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system-level memory optimization for high-level synthesis of component-based SoCs  14
System-level memory optimization for high-level synthesis of...
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2014 international conference on hardware/software codesign and system synthesis, CODES+ISSS 2014
作者: Pilato, Christian Mantovani, Paolo Di Guglielmo, Giuseppe Carloni, Luca P. Department of Computer Science Columbia University New YorkNY United States
The design of specialized accelerators is essential to the success of many modern systems-on-Chip. Electronic system-level design methodologies and high-level synthesis tools are critical for the efficient design and ... 详细信息
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Attention-Based Secure Feature Extraction in Near Sensor Processing: Work-in-Progress
Attention-Based Secure Feature Extraction in Near Sensor Pro...
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international conference on hardware/software codesign and system synthesis (CODES+ISSS)
作者: Bhowmik, Pankaj Pantho, Md Jubaer Hossain Saha, Sujan Kumar Bobda, Christophe Univ Florida Dept Elect & Comp Engn Gainesville FL 32611 USA
This paper presents a secure hardware architecture of an image sensor to accelerate feature extraction using region-level parallelism. For each logical region, the design includes a region processing unit (RPU) with a... 详细信息
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A system-level methodology for fully compensating process variability impact of memory organizations in periodic applications  05
A system-level methodology for fully compensating process va...
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international conference on hardware/software codesign and system synthesis
作者: Papanikolaou, A Lobmaier, F Wang, H Miranda, M Catthoor, F IMEC vzw Louvain Belgium
Process variability is an emerging problem that is becoming worse with each new technology node. Its impact on the performance and energy of memory organizations is severe and degrades the system-level parametric yiel... 详细信息
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Work-in-Progress: Offloading Cache Configuration Prediction to an FPGA for hardware Speedup and Overhead Reduction
Work-in-Progress: Offloading Cache Configuration Prediction ...
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Embedded systems Week / Int Conf on Compilers, Architecture, and synthesis for Embedded systems (CASES) / international conference on hardware/software codesign and system synthesis (CODES+ISSS) / Int Conf on Embedded software (EMSOFT)
作者: Vazquez, Ruben Gordon-Ross, Ann Stitt, Greg Univ Florida Dept Elect & Comp Engn Gainesville FL 32611 USA
In this paper, we present our cache configuration prediction methodology offloaded to an FPGA for improved performance and hardware overhead reduction, while maintaining cache configuration predictions within 5% of th... 详细信息
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system-level power and timing variability characterization to compute thermal guarantees  11
System-level power and timing variability characterization t...
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Embedded systems Week 2011, ESWEEK 2011 - 9th IEEE/ACM international conference on hardware/software-codesign and system synthesis, CODES+ISSS'11
作者: Kumar, Pratyush Thiele, Lothar Computer Engineering and Networks Laboratory ETH Zurich Switzerland
With ever-increasing power densities, temperature management using software and hardware techniques has become a necessity in the design of modern electronic systems. Such techniques have to be validated and optimized... 详细信息
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Enabling the High Level synthesis of Data Analytics Accelerators  16
Enabling the High Level Synthesis of Data Analytics Accelera...
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international conference on hardware/software codesign and system synthesis (CODES+ISSS)
作者: Minutoli, Marco Castellana, Vito Giovanni Tumeo, Antonino Lattuada, Marco Ferrandi, Fabrizio Pacific Northwest Natl Lab High Performance Comp Richland WA 99352 USA Politecn Milan Dipartimento Elettron Informaz & Bioingn I-20132 Milan Italy
Conventional High Level synthesis (HLS) tools mainly target compute intensive kernels typical of digital signal processing applications. We are developing techniques and architectural templates to enable HLS of data a... 详细信息
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Timing Analysis of Erroneous systems  14
Timing Analysis of Erroneous Systems
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international conference on hardware / software codesign and system synthesis (CODES+ISSS)
作者: Assare, Omid Gupta, Rajesh Univ Calif San Diego Dept Comp Sci & Engn La Jolla CA 92093 USA
Erroneous systems allow timing errors to occur during execution, but use measures to ensure continued operation through changes in operating parameters (voltage and frequency), error correction at various levels of th... 详细信息
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