检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

821 篇 会议
31 篇 期刊文献

馆藏范围

852 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

408 篇 工学
- 392 篇 计算机科学与技术...
- 319 篇 软件工程
- 82 篇 电子科学与技术（可...
- 59 篇 电气工程
- 42 篇 信息与通信工程
- 39 篇 控制科学与工程
- 9 篇 动力工程及工程热...
- 7 篇 机械工程
- 7 篇 光学工程
- 5 篇 材料科学与工程（可...
- 5 篇 建筑学
- 4 篇 土木工程
- 4 篇 安全科学与工程
- 3 篇 仪器科学与技术
- 3 篇 化学工程与技术
- 3 篇 航空宇航科学与技...
- 2 篇 力学（可授工学、理...
- 2 篇 环境科学与工程（可...
- 2 篇 生物医学工程（可授...
99 篇 理学
- 58 篇 数学
- 37 篇 系统科学
- 17 篇 物理学
- 8 篇 统计学（可授理学、...
- 2 篇 化学
55 篇 管理学
- 45 篇 管理科学与工程(可...
- 15 篇 工商管理
- 13 篇 图书情报与档案管...
5 篇 法学
- 4 篇 社会学
- 1 篇 法学
3 篇 经济学
- 3 篇 应用经济学
1 篇 医学
1 篇 艺术学

主题

167 篇 hardware
94 篇 computer archite...
76 篇 embedded system
58 篇 application soft...
56 篇 permission
50 篇 embedded systems
47 篇 system-on-a-chip
45 篇 software
44 篇 algorithm design...
42 篇 computational mo...
41 篇 energy consumpti...
41 篇 field programmab...
35 篇 costs
34 篇 system-on-chip
32 篇 space exploratio...
30 篇 high level synth...
29 篇 system-level des...
27 篇 timing
26 篇 delay
25 篇 embedded softwar...

机构

8 篇 center for embed...
6 篇 school of comput...
6 篇 arizona state un...
6 篇 center for embed...
6 篇 department of co...
5 篇 school of inform...
5 篇 philips research...
5 篇 univ calif river...
5 篇 institute for in...
5 篇 department of el...
4 篇 department of co...
4 篇 university of er...
4 篇 tu braunschweig
4 篇 university of do...
4 篇 tensilica
4 篇 univ elect sci &...
4 篇 nec laboratories...
4 篇 philips research...
3 篇 integrated signa...
3 篇 east china norma...

作者

10 篇 ogras umit y.
9 篇 sri parameswaran
9 篇 nikil dutt
7 篇 rolf ernst
7 篇 parameswaran sri
7 篇 leupers rainer
6 篇 jiang wei
6 篇 dutt nikil
6 篇 robert p. dick
6 篇 mitra tulika
6 篇 rainer leupers
6 篇 andreas gerstlau...
5 篇 pasricha sudeep
5 篇 gerd ascheid
5 篇 greg stitt
5 篇 jinyu zhan
5 篇 umit y. ogras
5 篇 tei-wei kuo
5 篇 wei jiang
5 篇 yuan-hao chang

语言

849 篇 英文
3 篇 其他
1 篇 中文

检索条件"任意字段=2024 International Conference on Hardware/Software Codesign and System Synthesis"

共 852 条记录，以下是101-110 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

Memory accesses management during high level synthesis

Memory accesses management during high level synthesis

引用

2nd international conference on hardware/software codesign and systems synthesis

作者： Corre, G Senn, E Bomel, P Julien, N Martin, E Univ S Brittany LESTER F-56321 Lorient France

ISBN: (纸本)1581139373

We introduce a new approach to take into account the memory architecture and the memory mapping in behavioral synthesis. We formalize the memory mapping as a set of constraints for the synthesis, and defined a Memory Constraint Graph and an accessibility criterion to be used in the scheduling step. We present a new strategy for implementing signals (ageing vectors). We formalize the maturing process and explain how it may generate memory conflicts over several iterations of the algorithm. The final Compatibility Graph indicates the set of valid mappings for every signal. Several experiments are performed with our HLS tool GAUT. Our scheduling algorithm exhibits a relatively low complexity that permits to tackle complex designs in a reasonable time.

关键词： memory aware behavioral synthesis

来源：评论

学校读者我要写书评

暂无评论

Cellular handset technology system requirements and integration trends

Cellular handset technology system requirements and integrat...

引用

2nd international conference on hardware/software codesign and systems synthesis

作者： Mattisson, S Ericsson Mobile Platforms AB Strateg Prod Management Analog Syst Design SE-22183 Lund Sweden

ISBN: (纸本)1581139373

In ten years the cellular telephone has evolved from a tool for the professional to an indispensable consumer product with a very high market penetration. At the same time, the handset cost, weight, and standby time have been reduced by more than a factor of ten. These factors have been critical for the success story of the mobile phone. The technical aspects behind the rapid handset evolution are discussed. In particular, what advances in the radio architecture, for example the zero-IF GSM receiver, the baseband (CMOS) technology, and the radio system design areas have meant for the reduction of size, weight, cost, and power consumption is discussed. Future challenges, like SW-DSP-digital-RF partitioning, linear multi-mode modulation with high linearity requirements, digital leakage issues, and power consumption limitations in multimedia handsets are discussed with future generation handsets in mind.

关键词： Cellular telephone systems

来源：评论

学校读者我要写书评

暂无评论

Work-in-Progress: AMVP - A High Performance Virtual Platform using Parallel systemC for Multicore ARM Architectures

Work-in-Progress: AMVP - A High Performance Virtual Platform...

引用

ACM/IEEE international conference on hardware/software codesign and system synthesis (CODES+ISSS)

作者： Weinstock, Jan Henrik Bucs, Robert Lajos Walbroel, Florian Leupers, Rainer Ascheid, Gerd Rhein Westfal TH Aachen Aachen Germany

ISBN: (纸本)9781538655627

This paper presents AMVP - a systemC based simulator for ARM multicore platforms designed as a tool for early SW development during platform bring-up. It uses a parallel systemC simulation approach to counter the performance slowdown incurred when simulating multi-processor designs. AMVP is sufficiently detailed to support running and debugging unmodified SW images of popular benchmark applications and modern OS kernels like Linux.

关键词： Electronic system Level Parallel Discrete Event Simulation Parallel systemC Simulation

来源：评论

学校读者我要写书评

暂无评论

system-level memory optimization for high-level synthesis of component-based SoCs 14

System-level memory optimization for high-level synthesis of...

引用

2014 international conference on hardware/software codesign and system synthesis, CODES+ISSS 2014

作者： Pilato, Christian Mantovani, Paolo Di Guglielmo, Giuseppe Carloni, Luca P. Department of Computer Science Columbia University New YorkNY United States

ISBN: (纸本)9781450330510

The design of specialized accelerators is essential to the success of many modern systems-on-Chip. Electronic system-level design methodologies and high-level synthesis tools are critical for the efficient design and optimization of an accelerator. Still, these methodologies and tools offer only limited support for the optimization of the memory structures, which are often responsible for most of the area occupied by an accelerator. To address these limitations, we present a novel methodology to automatically derive the memory subsystems of SoC accelerators. Our approach enables compositional design-space exploration and promotes design reuse of the accelerator specifications. We illustrate its effective-ness by presenting experimental results on the design of two accelerators for a high-performance embedded application. Copyright 2014 ACM.

关键词： system-on-chip

来源：评论

学校读者我要写书评

暂无评论

Attention-Based Secure Feature Extraction in Near Sensor Processing: Work-in-Progress

Attention-Based Secure Feature Extraction in Near Sensor Pro...

引用

international conference on hardware/software codesign and system synthesis (CODES+ISSS)

作者： Bhowmik, Pankaj Pantho, Md Jubaer Hossain Saha, Sujan Kumar Bobda, Christophe Univ Florida Dept Elect & Comp Engn Gainesville FL 32611 USA

ISBN: (纸本)9781728191980

This paper presents a secure hardware architecture of an image sensor to accelerate feature extraction using region-level parallelism. For each logical region, the design includes a region processing unit (RPU) with an attention module (AM). The AM activates the processing in the RPU if there are no spatiotemporal redundancies. It reduces power consumption and data volume by utilizing the concepts of predictive coding. Also, every RPU has a crypto-core driven by the AM to withstand against adversaries. Simulation results show we can save 89.70% power with a significant speedup.

关键词： Pixel Level Processing SIFT Attention Module Image Sensor hardware security FPGA ASIC

来源：评论

学校读者我要写书评

暂无评论

A system-level methodology for fully compensating process variability impact of memory organizations in periodic applications 05

A system-level methodology for fully compensating process va...

引用

international conference on hardware/software codesign and system synthesis

作者： Papanikolaou, A Lobmaier, F Wang, H Miranda, M Catthoor, F IMEC vzw Louvain Belgium

ISBN: (纸本)1595931619

Process variability is an emerging problem that is becoming worse with each new technology node. Its impact on the performance and energy of memory organizations is severe and degrades the system-level parametric yield. In this paper we propose a broadly applicable system-level technique that can guarantee parametric yield on the memory organization and which minimizes the energy overhead associated to variability in the conventional design process. It is based on offering configuration capabilities at the memory-level and exploiting them at the system-level. This technique can decrease by up to a factor of 5 the energy overhead that is introduced by state-of-the-art process variability compensation techniques, including statistical timing analysis. In this way we obtain results close to the ideal nominal design again.

关键词： process variability system-level compensation parametric yield

来源：评论

学校读者我要写书评

暂无评论

Work-in-Progress: Offloading Cache Configuration Prediction to an FPGA for hardware Speedup and Overhead Reduction

Work-in-Progress: Offloading Cache Configuration Prediction ...

引用

Embedded systems Week / Int Conf on Compilers, Architecture, and synthesis for Embedded systems (CASES) / international conference on hardware/software codesign and system synthesis (CODES+ISSS) / Int Conf on Embedded software (EMSOFT)

作者： Vazquez, Ruben Gordon-Ross, Ann Stitt, Greg Univ Florida Dept Elect & Comp Engn Gainesville FL 32611 USA

In this paper, we present our cache configuration prediction methodology offloaded to an FPGA for improved performance and hardware overhead reduction, while maintaining cache configuration predictions within 5% of th... 详细信息

ISBN: (纸本)9781450369237

关键词： cache configurable artificial neural network mobile devices FPGA phases machine learning

来源：评论

学校读者我要写书评

暂无评论

system-level power and timing variability characterization to compute thermal guarantees 11

System-level power and timing variability characterization t...

引用

Embedded systems Week 2011, ESWEEK 2011 - 9th IEEE/ACM international conference on hardware/software-codesign and system synthesis, CODES+ISSS'11

作者： Kumar, Pratyush Thiele, Lothar Computer Engineering and Networks Laboratory ETH Zurich Switzerland

ISBN: (纸本)9781450307154

With ever-increasing power densities, temperature management using software and hardware techniques has become a necessity in the design of modern electronic systems. Such techniques have to be validated and optimized with respect to the thermal guarantee they provide, i.e., a safe upperbound on the peak temperature of the system under all operating conditions. The computation of such a guarantee depends on the power and timing characteristics of the system. In this paper, we present formalisms to capture such characteristics at the system-level and provide an analytical technique to compute a provably safe upper-bound on the peak temperature. The proposed characterization and analysis is general in that it considers an impulse-responsebased thermal model, task-dependent power consumption, tasks with dynamic arrival patterns and variable resource demand, and a scheduling policy expressed as a hierarchical composition of several commonly used policies. Copyright 2011 ACM.

关键词： Timing circuits

来源：评论

学校读者我要写书评

暂无评论

Enabling the High Level synthesis of Data Analytics Accelerators 16

Enabling the High Level Synthesis of Data Analytics Accelera...

引用

international conference on hardware/software codesign and system synthesis (CODES+ISSS)

作者： Minutoli, Marco Castellana, Vito Giovanni Tumeo, Antonino Lattuada, Marco Ferrandi, Fabrizio Pacific Northwest Natl Lab High Performance Comp Richland WA 99352 USA Politecn Milan Dipartimento Elettron Informaz & Bioingn I-20132 Milan Italy

ISBN: (纸本)9781450344838

Conventional High Level synthesis (HLS) tools mainly target compute intensive kernels typical of digital signal processing applications. We are developing techniques and architectural templates to enable HLS of data analytics applications. These applications are memory intensive, present fine-grained, unpredictable data accesses, and irregular, dynamic task parallelism. We discuss an architectural template based around a distributed controller to efficiently exploit thread level parallelism. We present a memory interface that supports parallel memory subsystems and enables implementing atomic memory operations. We introduce a dynamic task scheduling approach to efficiently execute heavily unbalanced workload. The templates are validated by synthesizing queries from the Lehigh University Benchmark (LUBM), a well know SPARQL benchmark.

关键词： High level synthesis

来源：评论

学校读者我要写书评

暂无评论

Timing Analysis of Erroneous systems 14

Timing Analysis of Erroneous Systems

引用

international conference on hardware / software codesign and system synthesis (CODES+ISSS)

作者： Assare, Omid Gupta, Rajesh Univ Calif San Diego Dept Comp Sci & Engn La Jolla CA 92093 USA

ISBN: (纸本)9781450330510

Erroneous systems allow timing errors to occur during execution, but use measures to ensure continued operation through changes in operating parameters (voltage and frequency), error correction at various levels of the system, or ensuring controlled occurrence of errors to perform approximate computing. In this paper, we are interested in characterization of error behavior at the level of instructions and programs. We propose Inter- and Intra-Program Variation as measures of error rate variability in different programs and among instructions of a program, respectively. We also characterize the error rate variation caused by the program input data and show that it is comparable to other sources of variability such as process variation. Finally, we present an analysis of the physical location of errors in hardware, identify regions in which most of the errors occur, and how different programs change the distribution of errors among these regions. In order to enable reliable timing analysis of large programs, we propose Clustered Timing Model (CTM), a high level timing model based on clustering functionally similar timing paths of the processor, and develop a CTM for LEON3, a representative in-order RISC processor. The accuracy of the model is verified using our variation-aware timing analysis framework with an average error of 3.9% (max. 6.7%) across a wide range of voltage-temperature corners.

关键词： erroneous systems variability process variation delay faults variation-aware timing analysis dynamic error estimation and software error behavior

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共86页 << < 7 8 9 10 11 12 13 14 15 16 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：