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CODES+ISSS 2006: 4th international conference on hardware software codesign and system synthesis

作者： So, Hayden Kwok-Hay Tkachenko, Artem Brodersen, Robert Department of Electrical Engineering and Computer Science University of California Berkeley

ISBN: (纸本)1595933700

This paper presents a hw/sw codesign methodology based on BORPH, an operating system designed for FPGA-based reconfigurable computers (RC's). By providing native kernel support for FPGA hardware, BORPH offers a homogeneous UNIX interface for both software and hardware processes. hardware processes inherit the same level of service from the kernel, such as file system support, as typical UNIX software processes. hardware and software components of a design therefore run as hardware and software processes within BORPH's run-time environment. The familiar and language independent UNIX kernel interface facilitates easy design reuse and rapid application development. Performance of our current implementation and our experience with developing a real-time wireless digital signal processing system based on BORPH will be presented. © Copyright 2006 ACM.

关键词： Field programmable gate arrays (FPGA)

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Formal Verification of GCSE in the Scheduling of High-level synthesis: Work-in-Progress

Formal Verification of GCSE in the Scheduling of High-level ...

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international conference on hardware/software codesign and system synthesis (CODES+ISSS)

作者： Hu, Jian Hu, Yongyang Yu, Long Wang, Wentao Yang, Haitao Kang, Yun Cheng, Jie Natl Univ Def Technol Res Inst 63 Nanjing Peoples R China Natl Univ Def Technol Coll Comp Sci & Technol Changsha Peoples R China

ISBN: (纸本)9781728191980

High-level synthesis entails application of a sequence of transformations to compile a high-level description of a hardware design (e.g., in C/C++/systemC) into a register-transfer level (RTL) implementation. However, an error may exist in the RTL implementation from the compiler in the high-level synthesis due to the complex and error prone compiling process. Global common subexpression elimination (GCSE) is a commonly used code motion technique in the scheduling of high-level synthesis. In this paper, we present an equivalence checking method to verify GCSE in the scheduling of high-level synthesis by enhancing the path equivalence criteria. The initial experimental results demonstrate our method can indeed verify the GCSE which has not been properly addressed in the past.

关键词： Equivalence Checking High-level synthesis FSMD Global Common Subexpression Elimination

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Dark Silicon as a Challenge for hardware/software Co-Design

Dark Silicon as a Challenge for Hardware/Software Co-Design

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international conference on hardware / software codesign and system synthesis (CODES+ISSS)

作者： Shafique, Muhammad Garg, Siddharth Mitra, Tulika Parameswaran, Sri Henkel, Joerg Karlsruhe Inst Technol CES Karlsruhe Germany Univ Waterloo Dept ECE Waterloo ON Canada Natl Univ Singapore Sch Comp Singapore Singapore Univ New South Wales Sch Comp Sci & Engn Sydney NSW Australia

ISBN: (纸本)9781450330510

Dark Silicon refers to the observation that in future technology nodes, it may only be possible to power-on a fraction of on-chip resources (processing cores, hardware accelerators, cache blocks and so on) in order to stay within the power budget and safe thermal limits, while the other resources will have to be kept powered-off or "dark". In other words, chips will have an abundance of transistors, i.e., more than the number that can be simultaneously powered-on. Heterogeneous computing has been proposed as one way to effectively leverage this abundance of transistors in order to increase performance, energy efficiency and even reliability within power and thermal constraints. However, several critical challenges remain to be addressed including design, automated synthesis, design space exploration and run-time management of heterogeneous dark silicon processors. The hardware/software co-design and synthesis community has potentially much to contribute in solving these new challenges introduced by dark silicon and, in particular, heterogeneous computing. In this paper, we identify and highlight some of these critical challenges, and outline some of our early research efforts in addressing them.

关键词： hardware-software codesign power aware computing automated synthesis design space exploration energy efficiency improvement hardware-software co-design heterogeneous computing heterogeneous dark silicon processors on-chip resources performance improvement power budget power constraint reliability improvement run-time management safe thermal limits thermal constraint transistors Computer architecture hardware Program processors Reliability Silicon Switches hardware/software co-design power budget power aware computing Transistor Device Component Program processors Computer Architecture Silicon Switches performance boost Computer hardware Co-design Space Exploration

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Work-in-Progress: Co-Design of Security-Critical Real-Time systems to Prevent Fault Injection Attacks

Work-in-Progress: Co-Design of Security-Critical Real-Time S...

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ACM/IEEE international conference on hardware/software codesign and system synthesis (CODES+ISSS)

作者： Jiang, Wei Xiu, Liugen Zhan, Jinyu Jiang, Ke Univ Elect Sci & Technol China Sch Informat & Software Engn Chengdu Peoples R China Veoneer Res & Engn Dept Stockholm Sweden

ISBN: (纸本)9781538655627

We present a system-level co-design approach for security-critical real-time systems to resist fault injection attack. We focus on protecting the encryption/decryption of confidential messages over the internal communication in distributed real-time systems. To achieve the goal, we identify ten mechanisms of Fault Detection and Correction (FDC) and measure their corresponding time overheads and hardware overheads. We then make efforts to search for the best FDC schemes for protecting the message communication without violating the application deadline and hardware budget. We propose an efficient heuristic based on multi-objective evolutionary algorithms, which obtains better solutions with lower time complexity. Experiments demonstrate the superiority of the proposed technique.

关键词： Field programmable gate arrays Task analysis Cryptography Real-time systems Fault detection Resists

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Work-in-Progress: Hierarchical Ensemble Learning for Resource-Aware FPGA Computing

Work-in-Progress: Hierarchical Ensemble Learning for Resourc...

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ACM/IEEE international conference on hardware/software codesign and system synthesis (CODES+ISSS)

作者： Wang, Hongfei Li, Jianwen He, Kun Cai, Wenjie Huazhong Univ Sci & Technol Sch Comp Sci & Technol Wuhan Peoples R China

ISBN: (纸本)9781538655627

Recent years witness the rapid development in hardware/software codesign that integrates machine learning (ML) models with hardware systems [1]–[4]. Despite the booming trend in building neuromorphic computing systems [2], decision trees still attract much attention in ML communities, from both software [5], [6] and hardware [1], [7], [8] approaches. A single tree model may not be as accurate as desired. One effective way to remedy this is to apply ensemble methods [5]–[7], [9]–[11], such as the Random Forest (RF) [5]. Larger tree ensembles typically improve accuracy, but demand more computation resources, especially for hardware implementation. Many methods have been proposed to address this issue. The motivation arouses from the fact that tree models usually demands much less computation resource comparing to neural networks, making them extremely potential for wearable devices and embedded systems at the edge nodes of the IoT [7], [11], [12]. Moreover, due to their inherent structures, tree ensembles are ideal for exploiting the computational parallelism on FPGA [1], [4], [7]–[9], [11], [13].

关键词： Radio frequency Vegetation hardware Field programmable gate arrays Forestry Minimization Computational modeling

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A Low Cost Acceleration Method for hardware Trojan Detection Based on Fan-out Cone Analysis 14

A Low Cost Acceleration Method for Hardware Trojan Detection...

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international conference on hardware / software codesign and system synthesis (CODES+ISSS)

作者： Zhou, Bin Zhang, Wei Thambipillai, Srikanthan Teo, J. K. J. Nanyang Technol Univ Sch Comp Engn Singapore Singapore Hong Kong Univ Sci & Technol Dept Elect & Comp Engn Hong Kong Peoples R China Harbin Inst Technol Res Ctr Basic Space Sci Harbin Heilongjiang Peoples R China

ISBN: (纸本)9781450330510

Fabless semiconductor industry and government agencies have raised serious concerns about tampering with inserting hardware Trojans in an integrated circuit supply chain in recent years. In this paper, a low hardware overhead acceleration method of the detection of HTs based on the insertion of 2-to-1 MUXs as test points is proposed. In the proposed method, the fact that one logical gate has a significant impact on the transition probability of the logical gates in its logical fan-out cone is utilized to optimize the number of the insertion MUXs. The nets which have smaller transition probability than the threshold value set by the user and minimal logical depth from the primary inputs are selected as the candidate nets. As for each candidate net, only its input net with smallest signal probability is required to be inserted the MUXs based test points until the minimal transition probability of the entire circuit is no smaller than the threshold value. Experiment results on ISCAS'89 benchmark circuits show that our proposed method can achieve remarkable improvement of transition probability with small overhead penalty.

关键词： hardware Trojan Fan-out cone Low cost Signal probability Transition probability

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Proceedings of the ninth international symposium on hardware/software codesign

Proceedings of the ninth international symposium on hardware...

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9th international Symposium on hardware/software codesign

The proceedings contains 43 papers from the conference on the Proceedings of the Ninth international Symposium on hardware/software codesign. Topic discussed include: the usage of stochastic processes in embedded system specifications;modelling and evaluation of hardware/software designs;a practical toolbox for system level communication synthesis;designing domain-specific processors;a novel parallel deadlock detection algorithm and architecture;towards effective embedded processors in codesigns: customizable partitioned caches;and development cost and size estimation starting from high-level specifications.

关键词： Embedded systems

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system-level power-performance tradeoffs for reconfigurable computing

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) systemS 2006年第7期14卷 730-739页

作者： Noguera, Juanjo Badia, Rosa M. Tech Univ Catalonia Comp Architecture Dept Barcelona 08034 Spain

In this paper, we propose a configuration-aware data-partitioning approach for reconfigurable computing, We show how the reconfiguration overhead impacts the data-partitioning process. Moreover, we explore the system-level power-performance tradeoffs available when implementing streaming embedded applications on fine-grained reconfigurable architectures. For a certain group of streaming applications, we show that an efficient hardware/software partitioning algorithm is required when targeting low power. However, if the application objective is performance, then we propose the use of dynamically reconfigurable architectures. We propose a design methodology that adapts the architecture and algorithms to the application requirements. The methodology hag been proven to work on a real research platform based on Xilinx devices. Finally, we have applied our methodology, and algorithms to the case study of image sharpening, which is required nowadays in digital cameras and mobile phones.

关键词： hardware/software (HW/SW) codesign power-performance tradeoffs reconfigurable computing (RC)

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Heatmap-Aware Low-Cost Design to Resist Adversarial Attacks: Work-in-Progress

Heatmap-Aware Low-Cost Design to Resist Adversarial Attacks:...

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international conference on hardware/software codesign and system synthesis (CODES+ISSS)

作者： He, Zhiyuan Jiang, Wei Zhan, Jinyu Wang, Xupeng We, Xiangyu Univ Elect Sci & Technol China Sch Informat & Software Engn Chengdu Peoples R China

ISBN: (纸本)9781728191980

It is a challenging task to resist adversarial attacks due to the imperceptibility of adversarial examples. The passive defense method is developed based on a series of input transformations and has achieved a promising result, which however suffers from a high computation cost. In this paper, we design a new heatmap-aware method to defend adversarial attacks, leading to a significant decrease in the time cost. To he specific, we compute the classification importance from each part of the input to obtain the heatmap of the data, and the key areas of classification are extracted according to the heatmap. A series of transformations are applied to the key areas of the classification, which reduces the amount of data to be processed and thus reduces the time cost. A set of preliminary experiments are conducted to testify the effectiveness of the proposed approach.

关键词： Costs

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Fast Online synthesis of Generally Programmable Digital Microfluidic Biochips 12

Fast Online Synthesis of Generally Programmable Digital Micr...

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10th ACM international conference on hardware/software-codesign and system synthesis

作者： Grissom, Daniel Brisk, Philip Univ Calif Riverside Dept Comp Sci & Engn Riverside CA 92521 USA

ISBN: (纸本)9781450314268

We introduce an online synthesis flow for digital microfluidic biochips, which will enable real-time response to errors and control flow. The objective of this flow is to facilitate fast assay synthesis while minimally compromising the quality of results. In particular, we show that a virtual topology, which constrains the allowable locations of assay operations such as mixing, dilution, sensing, etc., in lieu of traditional placement, can significantly speed up the synthesis process without significantly lengthening assay execution time.

关键词： Microfluidics Laboratory-on-Chip (LoC) Electrowetting-on-Dielectric (EWoD) synthesis

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