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检索条件"任意字段=2024 International Conference on Hardware/Software Codesign and System Synthesis"
853 条 记 录,以下是101-110 订阅
排序:
A unified hardware/software runtime environment for FPGA-based reconfigurable computers using BORPH
A unified hardware/software runtime environment for FPGA-bas...
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CODES+ISSS 2006: 4th international conference on hardware software codesign and system synthesis
作者: So, Hayden Kwok-Hay Tkachenko, Artem Brodersen, Robert Department of Electrical Engineering and Computer Science University of California Berkeley
This paper presents a hw/sw codesign methodology based on BORPH, an operating system designed for FPGA-based reconfigurable computers (RC's). By providing native kernel support for FPGA hardware, BORPH offers a ho... 详细信息
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Formal Verification of GCSE in the Scheduling of High-level synthesis: Work-in-Progress
Formal Verification of GCSE in the Scheduling of High-level ...
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international conference on hardware/software codesign and system synthesis (CODES+ISSS)
作者: Hu, Jian Hu, Yongyang Yu, Long Wang, Wentao Yang, Haitao Kang, Yun Cheng, Jie Natl Univ Def Technol Res Inst 63 Nanjing Peoples R China Natl Univ Def Technol Coll Comp Sci & Technol Changsha Peoples R China
High-level synthesis entails application of a sequence of transformations to compile a high-level description of a hardware design (e.g., in C/C++/systemC) into a register-transfer level (RTL) implementation. However,... 详细信息
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Dark Silicon as a Challenge for hardware/software Co-Design
Dark Silicon as a Challenge for Hardware/Software Co-Design
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international conference on hardware / software codesign and system synthesis (CODES+ISSS)
作者: Shafique, Muhammad Garg, Siddharth Mitra, Tulika Parameswaran, Sri Henkel, Joerg Karlsruhe Inst Technol CES Karlsruhe Germany Univ Waterloo Dept ECE Waterloo ON Canada Natl Univ Singapore Sch Comp Singapore Singapore Univ New South Wales Sch Comp Sci & Engn Sydney NSW Australia
Dark Silicon refers to the observation that in future technology nodes, it may only be possible to power-on a fraction of on-chip resources (processing cores, hardware accelerators, cache blocks and so on) in order to... 详细信息
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Work-in-Progress: Co-Design of Security-Critical Real-Time systems to Prevent Fault Injection Attacks
Work-in-Progress: Co-Design of Security-Critical Real-Time S...
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ACM/IEEE international conference on hardware/software codesign and system synthesis (CODES+ISSS)
作者: Jiang, Wei Xiu, Liugen Zhan, Jinyu Jiang, Ke Univ Elect Sci & Technol China Sch Informat & Software Engn Chengdu Peoples R China Veoneer Res & Engn Dept Stockholm Sweden
We present a system-level co-design approach for security-critical real-time systems to resist fault injection attack. We focus on protecting the encryption/decryption of confidential messages over the internal commun... 详细信息
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Work-in-Progress: Hierarchical Ensemble Learning for Resource-Aware FPGA Computing
Work-in-Progress: Hierarchical Ensemble Learning for Resourc...
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ACM/IEEE international conference on hardware/software codesign and system synthesis (CODES+ISSS)
作者: Wang, Hongfei Li, Jianwen He, Kun Cai, Wenjie Huazhong Univ Sci & Technol Sch Comp Sci & Technol Wuhan Peoples R China
Recent years witness the rapid development in hardware/software codesign that integrates machine learning (ML) models with hardware systems [1]–[4]. Despite the booming trend in building neuromorphic computing system... 详细信息
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A Low Cost Acceleration Method for hardware Trojan Detection Based on Fan-out Cone Analysis  14
A Low Cost Acceleration Method for Hardware Trojan Detection...
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international conference on hardware / software codesign and system synthesis (CODES+ISSS)
作者: Zhou, Bin Zhang, Wei Thambipillai, Srikanthan Teo, J. K. J. Nanyang Technol Univ Sch Comp Engn Singapore Singapore Hong Kong Univ Sci & Technol Dept Elect & Comp Engn Hong Kong Peoples R China Harbin Inst Technol Res Ctr Basic Space Sci Harbin Heilongjiang Peoples R China
Fabless semiconductor industry and government agencies have raised serious concerns about tampering with inserting hardware Trojans in an integrated circuit supply chain in recent years. In this paper, a low hardware ... 详细信息
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Proceedings of the ninth international symposium on hardware/software codesign
Proceedings of the ninth international symposium on hardware...
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9th international Symposium on hardware/software codesign
The proceedings contains 43 papers from the conference on the Proceedings of the Ninth international Symposium on hardware/software codesign. Topic discussed include: the usage of stochastic processes in embedded syst... 详细信息
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system-level power-performance tradeoffs for reconfigurable computing
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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) systemS 2006年 第7期14卷 730-739页
作者: Noguera, Juanjo Badia, Rosa M. Tech Univ Catalonia Comp Architecture Dept Barcelona 08034 Spain
In this paper, we propose a configuration-aware data-partitioning approach for reconfigurable computing, We show how the reconfiguration overhead impacts the data-partitioning process. Moreover, we explore the system-... 详细信息
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Heatmap-Aware Low-Cost Design to Resist Adversarial Attacks: Work-in-Progress
Heatmap-Aware Low-Cost Design to Resist Adversarial Attacks:...
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international conference on hardware/software codesign and system synthesis (CODES+ISSS)
作者: He, Zhiyuan Jiang, Wei Zhan, Jinyu Wang, Xupeng We, Xiangyu Univ Elect Sci & Technol China Sch Informat & Software Engn Chengdu Peoples R China
It is a challenging task to resist adversarial attacks due to the imperceptibility of adversarial examples. The passive defense method is developed based on a series of input transformations and has achieved a promisi... 详细信息
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Fast Online synthesis of Generally Programmable Digital Microfluidic Biochips  12
Fast Online Synthesis of Generally Programmable Digital Micr...
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10th ACM international conference on hardware/software-codesign and system synthesis
作者: Grissom, Daniel Brisk, Philip Univ Calif Riverside Dept Comp Sci & Engn Riverside CA 92521 USA
We introduce an online synthesis flow for digital microfluidic biochips, which will enable real-time response to errors and control flow. The objective of this flow is to facilitate fast assay synthesis while minimall... 详细信息
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