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检索条件"任意字段=2024 International Conference on Hardware/Software Codesign and System Synthesis"

共 853 条记录，以下是101-110 订阅

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Toward Automating Cooja Experiment Workflows for Dataset Generation

Toward Automating Cooja Experiment Workflows for Dataset Gen...

引用

international conference on software Defined systems (SDS)

作者： Greta Grigoryan Hrant Khachatrian Theofanis P. Raptis Yerevan State University Yerevan Armenia YerevaNN Yerevan Armenia Institute of Informatics and Telematics National Research Council Pisa Italy

ISBN: (数字)9798331518325

ISBN: (纸本)9798331518332

The development of Internet of Things (IoT) applications requires rigorous testing and validation, often facilitated by simulation environments. These environments abstract real-world systems, enabling the synthesis and automation of complex experiments without the need for direct interaction with physical hardware. Cooja, an extensible and versatile IoT simulator within the Contiki operating system, supports the emulation of diverse network topologies and protocols, making it an essential tool for IoT research. However, Cooja lacks an end-to-end automated experiment generation and management mechanism, necessitating manual configuration and management that can be both labor-intensive and error-prone. This paper presents an initial design and implementation of an automated system for experiment generation and management within Cooja. Our approach aims to streamline experimental workflows, enhance efficiency, and reduce the overhead associated with manual processes. This work represents a significant step toward fully automating IoT experiment workflows in Cooja, fostering more efficient and reliable IoT research and development.

关键词： Automation systematics Network topology Manuals software Internet of Things Reliability Research and development Testing Radiofrequency interference

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Performance Test of Holographic Video Communication system

Performance Test of Holographic Video Communication System

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Multimedia Computing, Networking and Applications (MCNA), international conference on

作者： Kübra Kara Jaime Lloret Oscar Romero Sandra Sendra C/Paranimf 1 Grao de Gandia Instituto de Investigación para la Gestión Integrada de Zonas Costeras Universitat Politècnica de València Valencia Spain

ISBN: (数字)9798350354737

ISBN: (纸本)9798350354744

Holography creates three-dimensional (3D) images with depth and relief, and can be applied to medicine, engineering, and entertainment, enabling holographic communication, live streaming, and virtual gatherings. Digital holography involves using digital displays, cameras, and beams. This paper discusses various holographic systems, including computational holography, which uses computers to produce 3D images, Deep Holography (DH), which utilizes deep neural networks (DNN), and tensor holography, which combines DNN and machine learning (ML) to produce 3D images in mid-air. This paper also addresses network challenges, such as the high data transmission, bandwidth limitations that can hinder the quality of the holographic image, and the low latency crucial for maintaining real-time interaction in holographic communication. While some scholars introduce the capacities of 6 G networks, other authors propose a compression and differentiated prioritization technique. Holography can create striking images using convolutional neural networks (CNN) and an anti-aliasing double-phase (AA-DPM) method. Based on the communication performance test that has been carried out, it can be concluded that ensuring access to powerful and optimized hardware and software is crucial for both text and holographic image generation. As the complexity and length of the text increase, processing time augments as well. There are significant differences between using powerful servers and weaker hardware. Finally, it can be concluded that it is imperative to prioritize hardware and software for image generation to facilitate a smooth conversation.

关键词： Three-dimensional displays Tensors Image synthesis Bandwidth Holography Streaming media hardware software Convolutional neural networks Servers

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16-Bit SABP: Quasi-Stochastic Data Representation Unit for AI hardware Using FPGA

16-Bit SABP: Quasi-Stochastic Data Representation Unit for A...

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IEEE international SOC conference

作者： Marwan A. Abdelfattah Hossam O. Ahmed Mohamed A. Abdelghany Computer Science and Engineering Department German University in Cairo Egypt College of Engineering and Technology American University of the Middle East Egaila Kuwait Electronics and Engineering Department German University in Cairo Egypt

ISBN: (数字)9798350377569

ISBN: (纸本)9798350377576

Efficient data representation is a cornerstone in various domains such as Artificial Intelligence (AI), image processing, and video processing. Discovering the optimal data representation is key to enhancing interfacing, reducing computational complexity, and minimizing power consumption, particularly for digital hardware platforms. This paper presents three modifications to the state-of-the-art 10-bit Bent-Pyramid system, known for its quasi-stochastic data representation. We propose an upgrade to a 16-bit Bent Pyramid (BP), aiming to achieve a higher dynamic range resolution. These proposed three phases are the 16-bit Bent Pyramid (BP), the 16-bit Shifted Bent Pyramid (SBP), and the 16-bit Shifted Asserted Bent Pyramid (SABP). Throughout these modification stages, the latest version of BSA-BP effectively decreases the maximum multiplication error to an impressive $8.2 \%$ in a single multiplication instance, as opposed to $9 \%$ in two multiplication instances observed in the state-of-the-art research. The SABP architecture has been designed using VHDL, and the targeted FPGA was the Intel Cyclone V 5CGXFC9D6F27C7 chip. According to the synthesis findings of the Intel Quartus Prime software, the maximum operating frequency is 969.93 MHz, and there is only 7.02 mW of total thermal power dissipation per SABP block. The suggested 16-bit SABP demonstrated a lower maximum error rate drop of $\mathbf{8 . 8 9 \%}$ and $\mathbf{7 . 8 6 \%}$, respectively, in contrast to the cutting-edge 10bit BP and the 16-bit SC.

关键词： VHDL Image processing system performance Data visualization Dynamic range hardware software system-on-chip Artificial intelligence Field programmable gate arrays

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Work-in-Progress: Improving Security and Maintainability in Modular Embedded systems with hardware Support

Work-in-Progress: Improving Security and Maintainability in ...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Maja Malenko Leandro Batista Ribeiro Marcel Baunach Graz University of Technology Austria

ISBN: (纸本)9781665417242

The current trend of transforming static embedded systems into open platforms (in which several software providers are able to directly load their software) drives the need to design and implement modular embedded software. Additionally, a myriad of embedded devices are expected to operate and provide services for years, or even decades, while remaining correct and secure at all times. Therefore, one of the emerging challenges for highly adaptive embedded computing platforms is to offer dynamic software composition at runtime and internal device housekeeping, which in conjunction improve device maintainability. We propose a hardware/software co-designed technique to improve both security and maintainability in modular embedded systems.

关键词： Embedded computing Runtime Market research hardware Security Embedded software

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Work-in-Progress: A Study of Transistor Degradation in Cyber-Physical system Control Devices

Work-in-Progress: A Study of Transistor Degradation in Cyber...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Spencer Millican SueAnne Griffith Samuel Ginn College of Engineering Auburn University Auburn Alabama USA

ISBN: (纸本)9781665417242

This work presents a plan for investigating transistor aging and degradation in cyber physical systems under attack. The authors discuss the importance of such concerns, particularly with regard to negative bias temperature instability, and an approach to demonstrate the adverse effects of a cyber-attack resulting in premature aging of transistors within a system's digital controllers.

关键词： Degradation Negative bias temperature instability Thermal variables control Aging Cyber-physical systems Transistors

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Indoor Soft Decoration system Using Virtual Reality Technology

Indoor Soft Decoration System Using Virtual Reality Technolo...

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Distributed Computing and Electrical Circuits and Electronics (ICDCECE), IEEE international conference on

作者： Yingying Wang School of Art and Design Shandong Business Institute Yantai China

ISBN: (数字)9798350318609

ISBN: (纸本)9798350318616

In the information period, virtual reality technology has grown in popularity, especially in interior design. Users can engage with virtual exhibition halls without physically being in the scene, providing a unique and immersive experience. In this paper, a Virtual Reality (VR)-based virtual interior design system that divides into two categories including hardware- and software-based is presented. Preprocessing, model transformation, image fusion, and registration are the four stages of the system that are tested through simulation research. The suggested algorithm will determine when the region is constantly separated in advance time enhancing customer satisfaction, speeding up the display of interior design effects, and increasing coding efficiency. The objective is to provide target customers an immersive experience that enables them experience reality as close and real as possible at any time or location. This research presents the use of virtual reality technology in interior design for effect exhibition and system application analysis. This implemented algorithm has achieved 97 % of average similarity.

关键词： Industries Solid modeling Image synthesis Customer satisfaction Immersive experience Rendering (computer graphics) Encoding

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Work-in-Progress: The RISC-V Instruction Set Architecture Optimization and Fixed-point Math Library Co-design

Work-in-Progress: The RISC-V Instruction Set Architecture Op...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Meng Liu Faculty of Information Technology School of Microelectronics Beijing University of Technology Beijing China

ISBN: (纸本)9781665417242

In the field of IoT, RISC-V as an open-source instruction set shows great application potential. On the one hand, this is due to the low cost brought by the hardware open source trend. On the other hand, the modular instruction set architecture (ISA) design brings agile design ideas, and designers can pay more attention to the collaborative design of key ISA and software libraries. However, by analyzing the underlying mathematical assembly library, we found that the current RISC-V standard instruction set still has room for performance improvement for lightweight control mathematical operations. In this paper, we introduce a set of custom RISC-V ISA designs for fixed-point math libraries and perform performance evaluations to demonstrate the optimization results.

关键词： Performance evaluation software libraries Costs Instruction sets Computer architecture Market research hardware

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Work-in-Progress: Register File Management for PRET Machines

Work-in-Progress: Register File Management for PRET Machines

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Martin Koštál Michal Sojka Czech Technical University in Prague

ISBN: (纸本)9781665417242

PREcision Timed (PRET) machines often use multithreading to achieve high CPU resources utilisation and time-determinism. Multithreading enables sharing most of the pipeline resources between threads, except the register file (RF), which is used to store thread context. Traditional multithreading on PRET machines uses large RF. We propose a register file management (RFM) technique suitable for multithreaded PRET machines, reducing the RF size. Our RFM has software-controlled RF partitions for each thread with support for runtime repartitioning. We evaluate the design on the PRET uRISC processor with a 55% average reduction of FPGA resource utilisation and show performance tradeoff on a selection of TACLeBench benchmarks.

关键词： Radio frequency Runtime Multithreading Instruction sets Static analysis software Real-time systems

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Work-in-Progress: Early Power Estimation of CUDA-based CNNs on GPGPUs

Work-in-Progress: Early Power Estimation of CUDA-based CNNs ...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Christopher A. Metz Mehran Goli Rolf Drechsler University of Bremen Bremen Germany

ISBN: (纸本)9781665417242

The increasing application of Machine Learning (ML) techniques in the Internet of Things (IoT) devices has led designers to leverage ML accelerators like GPGPUs in such devices. However, choosing the most appropriate accelerator for such IoT devices is very challenging as they commonly should adhere to tight constraints e.g., low power consumption, long battery lifetime, and low cost of the final products. As a consequence, designing such application-specific IoT devices becomes a non-trivial and difficult task. In this paper, we present a novel approach to estimate power consumption of CUDA-based Convolutional Neural Networks (CNNs) on GPGPUs in the design phase. Our approach is able to provide designers with an early prediction of CNNs power consumption up to an absolute error of less than 2% in comparison to the real hardware execution.

关键词： Power demand Costs Estimation Machine learning hardware Batteries Internet of Things

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A Deep Learning-based Pest Insect Monitoring system for Ultra-low Power Pocket-sized Drones

A Deep Learning-based Pest Insect Monitoring System for Ultr...

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international conference on Distributed Computing in Sensor systems (DCOSS)

作者： Luca Crupi Luca Butera Alberto Ferrante Daniele Palossi Dalle Molle Institute for Artificial Intelligence (IDSIA) USI and SUPSI Lugano Switzerland Integrated Systems Laboratory (IIS) ETH Zürich Zürich Switzerland

ISBN: (数字)9798350369441

ISBN: (纸本)9798350369458

Smart farming and precision agriculture represent game-changer technologies for efficient and sustainable agribusiness. Miniaturized palm-sized drones can act as flexible smart sensors inspecting crops, looking for early signs of potential pest outbreaking. However, achieving such an ambitious goal requires hardware-software codesign to develop accurate deep learning (DL) detection models while keeping memory and computational needs under an ultra-tight budget, i.e., a few MB on-chip memory and a few 100s mW power envelope. This work presents a novel vertically integrated solution featuring two ultra-low power system-on-Chips (SoCs), i.e., the dual-core STM32H74 and a multi-core GWT GAP9, running two State-of-the-Art DL models for detecting the Popillia japonica bug. We fine-tune both models for our image-based detection task, quantize them in 8-bit integers, and deploy them on the two SoCs. On the STM32H74, we deploy a FOMO-MobileNetV2 model, achieving a mean average precision (mAP) of 0.66 and running at 16.1 frame/s within 498 mW. While on the GAP9 SoC, we deploy a more complex SSDLite-MobileNetV3, which scores an mAP of 0.79 and peaks at 6.8 frame/s within 33 mW. Compared to a top-notch RetinaNet-ResNet101-FPN full-precision baseline, which requires 14.9× more memory and 300× more operations per inference, our best model drops only 15% in mAP, paving the way toward autonomous palm-sized drones capable of lightweight and precise pest detection.

关键词： Smart agriculture Quantization (signal) Computational modeling Memory management Computer bugs Low power electronics Throughput

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