检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

821 篇 会议
31 篇 期刊文献

馆藏范围

852 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

408 篇 工学
- 392 篇 计算机科学与技术...
- 319 篇 软件工程
- 82 篇 电子科学与技术（可...
- 59 篇 电气工程
- 42 篇 信息与通信工程
- 39 篇 控制科学与工程
- 9 篇 动力工程及工程热...
- 7 篇 机械工程
- 7 篇 光学工程
- 5 篇 材料科学与工程（可...
- 5 篇 建筑学
- 4 篇 土木工程
- 4 篇 安全科学与工程
- 3 篇 仪器科学与技术
- 3 篇 化学工程与技术
- 3 篇 航空宇航科学与技...
- 2 篇 力学（可授工学、理...
- 2 篇 环境科学与工程（可...
- 2 篇 生物医学工程（可授...
99 篇 理学
- 58 篇 数学
- 37 篇 系统科学
- 17 篇 物理学
- 8 篇 统计学（可授理学、...
- 2 篇 化学
55 篇 管理学
- 45 篇 管理科学与工程(可...
- 15 篇 工商管理
- 13 篇 图书情报与档案管...
5 篇 法学
- 4 篇 社会学
- 1 篇 法学
3 篇 经济学
- 3 篇 应用经济学
1 篇 医学
1 篇 艺术学

主题

167 篇 hardware
94 篇 computer archite...
76 篇 embedded system
58 篇 application soft...
56 篇 permission
50 篇 embedded systems
47 篇 system-on-a-chip
45 篇 software
44 篇 algorithm design...
42 篇 computational mo...
41 篇 energy consumpti...
41 篇 field programmab...
35 篇 costs
34 篇 system-on-chip
32 篇 space exploratio...
30 篇 high level synth...
29 篇 system-level des...
27 篇 timing
26 篇 delay
25 篇 embedded softwar...

机构

8 篇 center for embed...
6 篇 school of comput...
6 篇 arizona state un...
6 篇 center for embed...
6 篇 department of co...
5 篇 school of inform...
5 篇 philips research...
5 篇 univ calif river...
5 篇 institute for in...
5 篇 department of el...
4 篇 department of co...
4 篇 university of er...
4 篇 tu braunschweig
4 篇 university of do...
4 篇 tensilica
4 篇 univ elect sci &...
4 篇 nec laboratories...
4 篇 philips research...
3 篇 integrated signa...
3 篇 east china norma...

作者

10 篇 ogras umit y.
9 篇 sri parameswaran
9 篇 nikil dutt
7 篇 rolf ernst
7 篇 parameswaran sri
7 篇 leupers rainer
6 篇 jiang wei
6 篇 dutt nikil
6 篇 robert p. dick
6 篇 mitra tulika
6 篇 rainer leupers
6 篇 andreas gerstlau...
5 篇 pasricha sudeep
5 篇 gerd ascheid
5 篇 greg stitt
5 篇 jinyu zhan
5 篇 umit y. ogras
5 篇 tei-wei kuo
5 篇 wei jiang
5 篇 yuan-hao chang

语言

849 篇 英文
3 篇 其他
1 篇 中文

检索条件"任意字段=2024 International Conference on Hardware/Software Codesign and System Synthesis"

共 852 条记录，以下是111-120 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

Metronomy: A Function-Architecture Co-simulation Framework for Timing Verification of Cyber-Physical systems 14

Metronomy: A Function-Architecture Co-simulation Framework f...

引用

international conference on hardware / software codesign and system synthesis (CODES+ISSS)

作者： Guo, Liangpeng Zhu, Qi Nuzzo, Pierluigi Passerone, Roberto Sangiovanni-Vincentelli, Alberto Lee, Edward A. Univ Calif Berkeley Berkeley CA 94720 USA Univ Calif Riverside Riverside CA 92521 USA Univ Trento Trento TN Italy

ISBN: (纸本)9781450330510

As the design complexity of cyber-physical systems continues to grow, modeling the system at higher abstraction levels with formal models of computation is increasingly appealing since it enables early design verification and analysis. One of the most important aspects in system modeling and analysis is timing. However, it is very challenging to analyze and verify timing at the early design stages, as the design representation is quite abstract and trade-offs have to be made between the performance requirements defined in terms of system functionality and the cost of the feasible architecture that can implement the functionality. In this paper, we present Metronomy, a function-architecture co-simulation framework that integrates functional modeling from Ptolemy and architectural modeling from the Metroll environment via a mapping interface. Metronomy exploits contract theory for timing verification and design space exploration via co-simulation. Two case studies on an electrical power system and a paper-feed sub-system for a high speed printing press demonstrate the effectiveness of our approach.

关键词： Cyber-Physical system Co-simulation Timing

来源：评论

学校读者我要写书评

暂无评论

Work-in-Progress: Equivalence of Transformations of Synchronous Data Flow Graphs

Work-in-Progress: Equivalence of Transformations of Synchron...

引用

ACM/IEEE international conference on hardware/software codesign and system synthesis (CODES+ISSS)

作者： Zhu, Xue-Yang Chinese Acad Sci State Key Lab Comp Sci Inst Software Beijing Peoples R China

ISBN: (纸本)9781538655627

Synchronous data flow graphs (SDFGs) are widely used to model digital signal processing (DSP) algorithms and streaming applications. Any valid SDFG can be converted to an equivalent homogenous SDFG (HSDFG). Retiming and unfolding are important graph transformation techniques for performance optimization of SDFGs. In this paper, we review the relationship among the three transformation techniques and reveal the equivalence of the combinations of them. The equivalence makes it possible to analyze and optimize SDFGs directly, without carrying out the explicit conversion procedures which are usually time and space-consuming.

关键词： IP networks Computational modeling Signal processing algorithms Processor scheduling Digital signal processing Optimization

来源：评论

学校读者我要写书评

暂无评论

A design methodology to implement memory accesses in high-level synthesis 11

A design methodology to implement memory accesses in high-le...

引用

Embedded systems Week 2011, ESWEEK 2011 - 9th IEEE/ACM international conference on hardware/software-codesign and system synthesis, CODES+ISSS'11

作者： Pilato, Christian Ferrandi, Fabrizio Sciuto, Donatella Dipartimento di Elettronica ed Informazione Politecnico di Milano Milano 20133 Italy

ISBN: (纸本)9781450307154

Nowadays, the memory synthesis is becoming the main bottleneck for the generation of efficient hardware accelerators. This paper presents a design methodology to efficiently and automatically implement memory accesses in High-Level synthesis. In particular, the approach starts from a behavioral specification (in pure C language) and a set of design constraints, such as the memory addresses where some of the data are stored. The methodology classifies which variables can be internally or externally allocated to the different modules to generate the proper architecture, fully supporting a wide range of C constructs, such as pointer arithmetic, function calls and array accesses. Moreover it allows to parallelize the accesses when the memory address is known at compile time, resulting in an efficient execution of the specification. Copyright 2011 ACM.

关键词： High level synthesis

来源：评论

学校读者我要写书评

暂无评论

Future challenges in embedded systems 04

Future challenges in embedded systems

引用

Second IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis, CODES+ISSS 2004

作者： Cuomo, Andrea Advanced System Technology ST Microelectronics

ISBN: (纸本)1581139373

Embedded systems will play a key role to drive the technological evolution in the next 20 years. Their evolution will further accelerate with the diffusion of the novel technologies that will deeply change our scenario, among which we can mention nanotechnologies, bioelectronics, and photonics. The central role of embedded systems in the economy will grow stronger and stronger: the starting point is the convergence between storage, security, video, audio, mobility and connectivity. systems are converging and ICs are more and more converging with systems: this poses a number of challenges for designers and technologists. A key issue is the definition of the right methodologies to translate system knowledge and competences into complex embedded systems, taking into account many system requirements and constraints. The key factor to win this challenge is to build the right culture. This means to be able to build the right environment to exploit existing design, architectural and technological solutions, and to favor the transfer of knowledge from one application field into another.

关键词： Embedded systems

来源：评论

学校读者我要写书评

暂无评论

software/hardware codesign of the Post Quantum Cryptography Algorithm NTRUEncrypt Using High-Level synthesis and Register-Transfer Level Design Methodologies 29

Software/Hardware Codesign of the Post Quantum Cryptography ...

引用

29th international conference on Field-Programmable Logic and Applications (FPL)

作者： Farahmand, Farnoud Duc Tri Nguyen Dang, Viet B. Ferozpuri, Ahmed Gaj, Kris George Mason Univ Dept Elect & Comp Engn Fairfax VA 22030 USA

ISBN: (纸本)9781728148847

When quantum computers become scalable and reliable, they are likely to break all public-key cryptography standards, such as RSA and Elliptic Curve Cryptography. The projected threat of quantum computers has led the U.S. National Institute of Standards and Technology (NIST) to an effort aimed at replacing existing public-key cryptography standards with new quantum-resistant alternatives. In December 2017, 69 candidates were accepted by NIST to Round 1 of the NIST Post-Quantum Cryptography (PQC) standardization process. NTRUEncrypt is one of the most well-known PQC algorithms that has withstood cryptanalysis. The speed of NTRUEncrypt in software, especially on embedded software platforms, is limited by the long execution time of its primary operation, polynomial multiplication. In this paper, we investigate speeding up NTRUEncrypt using software/hardware codesign on a Xilinx Zynq UltraScale+ multiprocessor system-on-chip (MPSoC). Polynomial multiplication is implemented in the Programmable Logic (PL) of Zynq using two approaches: traditional Register-Transfer Level (RTL) and High-Level synthesis (HLS). The remaining operations of NTRUEncrypt are executed in software on the Processing system (PS) of Zynq, using the bare-metal mode. The speed-up of our software/hardware codesigns vs. purely software implementations is determined experimentally and analyzed in the paper. The results are reported for the RTL-based and HLS-based hardware accelerators, and compared to the best available software implementation, included in the NIST submission package. The speed-ups for encryption were 2.4 and 3.9, depending on the selected parameter set. For decryption, the corresponding speed-ups were 4.0 and 6.8. In addition, for the polynomial multiplication operation itself, the speed up was in excess of 75. Our code for the NTRUEncrypt polynomial multiplier accelerator is being made open-source for further evaluation on multiple software/hardware platforms.

关键词： Post-Quantum Cryptography lattice-based NTRU hardware/software codesign High-Level synthesis

来源：评论

学校读者我要写书评

暂无评论

Highly-cited ideas in system codesign and synthesis 08

Highly-cited ideas in system codesign and synthesis

引用

Embedded systems Week 2008 - 6th IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis, CODES+ISSS 2008

作者： Vahid, Frank Givargis, Tony Department of Computer Science and Engineering University of California Riverside United States Center for Embedded Computer Systems UC Irvine United States Center for Embedded Computer Systems University of California Irvine United States

ISBN: (纸本)9781605584706

We conducted a study of citations of papers published between 1996 and 2006 in the CODES and ISSS conferences, representing the hardware/software codesign and system synthesis community. Citations, meaning non-self-citations only, were considered from all papers known to Google Scholar, as well as only from subsequent CODES/ISSS papers. We list the most-cited CODES/ISSS papers of each year, summarizing their topics, and discussing common features of those papers. For comparison purposes, we also measured citations for the computer architecture community's ISCA and MICRO conferences, and for the field-programmable gate array community's FPGA and FCCM conferences. We point out several interesting differences among the citation patterns of the three communities. Copyright 2008 ACM.

关键词： Computer architecture

来源：评论

学校读者我要写书评

暂无评论

A low-cost and low-power multi-standard video encoder

A low-cost and low-power multi-standard video encoder

引用

1st IEEE/ACM/IFIP international conference on Hardward/software codesign and system synthesis

作者： Llopis, RP Sethuraman, R Pinto, CA Peters, H Maul, S Oosterhuis, M Philips Res Labs NL-5656 AA Eindhoven Netherlands

ISBN: (纸本)1581137427

Video encoders are an important IP block in mobile multimedia systems. In this paper, we describe a low-cost low-power multi-standard (MPEG4, JPEG, and H.263) video/image encoder. The low-cost and low-power aspects are achieved by the right choice of algorithms and architectures. In the algorithm front, an embedded compression technique for reducing the size of loop memory has enabled a single-chip low-cost realization of the encoder. In the architectural front, an efficient hardware-software partitioning has contributed to the design of a low-power encoder. Further, the hardware components that accelerate the kernels of encoding are implemented as application specific instruction-set processors (ASIPs) thereby providing flexibility to address multi-standard encoding. The power and area estimates for the encoder for QCIF@15fps in 0.18mum CMOS technology are 30mW and 20mm(2) respectively including the loop memory.

关键词： video encoder multi-standard low-power low-cost ASIPs hardware/software partitioning

来源：评论

学校读者我要写书评

暂无评论

system-level design space exploration for three-dimensional (3D) SoCs 11

System-level design space exploration for three-dimensional ...

引用

Embedded systems Week 2011, ESWEEK 2011 - 9th IEEE/ACM international conference on hardware/software-codesign and system synthesis, CODES+ISSS'11

作者： Zou, Qiaosha Chen, Yibo Xie, Yuan Su, Alan Computer Science and Engineering Pennsylvania State University United States Synopsys Inc. Hsinchu Taiwan

ISBN: (纸本)9781450307154

Three-dimensional (3D) ICs promise to overcome barriers in integration density and interconnect scaling by leveraging fast, dense inter-die vias, thereby offering benefits of improved performance, higher memory bandwidth, smaller form factors, and heterogeneous integration. 3D integration provides additional architectural and technology-related design options for future system-on-chip (SoC) designs, making the early design space exploration more critical. This paper proposes a system-level design partition and hardware/ software co-synthesis framework for 3D SoC integration. The proposed methodology can be used to explore the enlarged design space and to find out the optimal design choices for given design constraints including form factor, performance, power, or yield. Copyright 2011 ACM.

关键词： system-on-chip

来源：评论

学校读者我要写书评

暂无评论

system-of-PUFs: Multilevel Security for Embedded systems 14

System-of-PUFs: Multilevel Security for Embedded Systems

引用

international conference on hardware / software codesign and system synthesis (CODES+ISSS)

作者： Konigsmark, S. T. Choden Hwang, Leslie K. Chen, Deming Wong, Martin D. F. Univ Illinois Dept Elect & Comp Engn Champaign IL 61820 USA

ISBN: (纸本)9781450330510

Embedded systems continue to provide the core for a wide range of applications, from smart-cards for mobile payment to smart-meters for power-grids. The resource and power dependency of embedded systems continues to be a challenge for state-of-the-art security practices. Moreover, even theoretically secure algorithms are often vulnerable in their implementation. With decreasing cost and complexity, physical attacks are an increasingly important threat. This threat led to the development of Physically Unclonable Functions (PUFs) which are disordered physical systems with various applications in hardware security. However, consistent security oriented design of embedded systems remains a challenge, as most formalizations and security models are concerned with isolated physical components or high-level concept. We provide four unique contributions: (i) We propose a system-level security model to overcome the chasm between secure components and requirements of high-level protocols;this enables synergy between component-oriented security formalizations and theoretically proven protocols. (ii) An analysis of current practices in PUF protocols using the proposed system-level security model;we identify significant issues and expose assumptions that require costly security techniques. (iii) A system-of-PUF (SoP) that utilizes the large PUF design-space to achieve security requirements with minimal resource utilization;SoP requires 64% less gate-equivalent units than recently published schemes. (iv) A multilevel authentication protocol based on SoP which is validated using our system-level security model and which overcomes current vulnerabilities. Furthermore, this protocol offers breach recognition and recovery.

关键词： Physically Unclonable Functions hardware Authentication

来源：评论

学校读者我要写书评

暂无评论

Exploring Compositional Neural Networks for Real-Time systems 22

Exploring Compositional Neural Networks for Real-Time System...

引用

22nd international conference on Formal Methods and Models for system Design

作者： Chatterjee, Sobhan Allen, Nathan Patel, Nitish Roop, Partha Univ Auckland Fac Engn Dept Elect Comp & Software Engn Auckland New Zealand

ISBN: (纸本)9798350378030;9798350378023

Real-time CPSs using Artificial Neural Networks (ANNs) are traditionally developed as monolithic black-boxes. This results in designs that are often difficult to formally verify against safety specifications and implement on hardware for formal timing analysis. Consequently, their implementation as a composition of smaller ANNs has received recent interest. These are easier to implement, parallelise and validate. Despite this, the question of how to produce hardware-implementable compositional designs from existing monolithic ones remains largely unanswered. This work develops a novel procedure to replace large ANN monolithic designs with smaller compositional designs and implement them on a Field Programmable Gate Array (FPGA) for timing analysis using synchronous compositional semantics. To illustrate our approach, we develop regression and classification ANN designs for multiple real-life datasets. Using various design and model architecture variations, we show that using a compositional design instead of a monolithic design can achieve an 85% reduction in WCET, around a 53% reduction in hardware resources and around a 40% reduction in computations and neuron connections for a minor reduction in performance.

关键词： Compositional Design FPGA hardware synthesis Lane Change Neural Network Neural Network Optimisation Neutal Network Composition

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共86页 << < 8 9 10 11 12 13 14 15 16 17 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：